Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-14
2003-07-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S636000
Reexamination Certificate
active
06593223
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming multilevel interconnects that are used to interconnect semiconductor devices. More particularly, the present invention relates to a method of forming a dual damascene structure.
2. Description of Related Art
Dual damascene structure is an ingenious design that forms embedded metallic interconnects within an insulating layer. The method of forming a dual damascene structure includes first forming an insulating layer over a substrate, and then planarizing the insulating layer. Thereafter, according to the required metallic line pattern and positions of via holes, the insulating layer is etched to form horizontal trenches and vertical vias. Next, metal is deposited over the substrate to fill the horizontal trenches and the vertical vias, thereby simultaneously forming metallic lines and vias.
Finally, a chemical-mechanical polishing (CMP) method is used to planarize the device surface. Unlike conventional processes, which first forms vias and then forms metallic lines in a photolithographic method, the present invention forms vias and metallic lines in a single operation. Hence, overlay errors or process bias due to mask misalignment can be avoided, and reliability of devices can be improved. Consequently, as the level of integration of devices increases, dual damascene structure is widely adopted in the semiconductor industry.
FIG. 1A through 1E
are cross-sectional views showing the progression of manufacturing steps in fabricating a dual damascene structure according to a conventional method. First, as shown in
FIG. 1A
, a substrate
100
having a metallic layer
102
thereon is provided. Next, an inter-metal dielectric (IMD)
104
is formed over the substrate and the metallic layer
102
, and then the IMD layer
104
is planarized. The inter-metal dielectric layer
104
can be a silicon oxide layer formed by a chemical vapor deposition method, and the IMD layer
104
can be planarized using a chemical-mechanical polishing method, for example. To prevent reflection from the metallic layer
102
in subsequent photolithographic operations which reflection may affect its resolution, an anti-reflection layer
105
is also formed over the IMD layer
104
.
Next, as shown in
FIG. 1B
, the anti-reflection layer
105
and the inter-metal dielectric layer
104
are patterned to form an opening
108
that exposes the metallic layer
102
. Typically, the method includes depositing photoresist over the anti-reflection layer
105
, and then patterning to form an opening in the photoresist layer
110
. Next, using the patterned photoresist layer
110
as a mask, the anti-reflection layer
105
and the IMD layer
104
are etched to form the opening
108
. Finally, the photoresist layer
110
is removed.
Thereafter, as shown in
FIGS. 1C and 1D
, the anti-reflection layer
105
and the IMD layer
104
are patterned again to form trenches
114
and
116
. Trench
114
is formed in a position above the metallic layer
102
, and trench
114
together with the residual opening
108
a
that leads to the metallic layer
102
form an opening
118
of the dual damascene structure. Generally, the method of forming the trenches includes depositing photoresist over the IMD layer
104
, and then patterning to form an opening in the photoresist layer
112
as shown in FIG.
1
C. Next, using the patterned photoresist layer
112
as a mask, the anti-reflection layer
105
and the IMD layer
104
are etched to form trenches
114
and
116
as shown in FIG.
1
D. Finally, the photoresist layer
112
is removed.
Subsequently, as shown in
FIG. 1E
, conductive material is deposited over the substrate
100
to fill the opening
118
and the trench
116
. Thereafter, the conductive layer is planarized to form a dual damascene structure
120
and a metallic line
122
. Conventionally, the conductive material can be aluminum or tungsten with a titanium/titanium nitride composite layer underneath serving as barrier layer/glue layer. However, in the operations as described in
FIGS. 1A through 1E
, there is no etching stop layer when the IMD layer
104
is etched to form the trenches
114
and
116
. Consequently, depth of trenches
114
and
116
is difficult to control, and hence ultimate electrical properties of devices can vary considerably.
FIGS. 2A through 2E
are cross-sectional views showing the progression of manufacturing steps in fabricating a dual damascene structure according to an alternative method. First, as shown in
FIG. 2A
, a substrate
200
having a first metallic layer
202
thereon is provided. Next, a dielectric layer
204
a
is formed over the substrate
200
, and then the dielectric layer
204
a
is planarized so that its thickness matches the depth of a via hole. Thereafter, a silicon nitride layer
206
that serves as an etching stop layer is formed over the dielectric layer
204
a.
Next, as shown in
FIG. 2B
, a photoresist layer
210
having an opening is formed over the silicon nitride layer
206
. In the subsequent step, using the patterned photoresist layer
210
as an etching mask, the silicon nitride layer
206
is etched to form an opening
208
. The opening
208
is formed where a via hole is desired. In other words, the opening
208
is formed directly above the metallic layer
202
.
Next, as shown in
FIG. 2C
, a second dielectric layer
204
b
and an anti-reflection layer
205
are sequentially formed over the substrate
200
. Thickness of the dielectric layer
204
b
has to be the same as the would-be thickness of the second metallic layer (metallic line) in the dual damascene structure.
Next, as shown in
FIG. 2D
, a photoresist layer
212
having an opening is formed over the anti-reflection layer
205
. Then, using the patterned photoresist layer
212
as an etching mask, the dielectric layer
204
b
is etched to form trenches
214
a
and
216
. Thereafter, using the silicon nitride layer
206
as an etching stop layer, the dielectric layer
204
a
is etched to form an opening
214
b
that exposes the first metallic layer
202
. Hence, the trench
214
a
and the opening
214
b
together form the opening
214
of a dual damascene structure.
Subsequently, as shown in
FIG. 2E
, the photoresist layer
212
is removed. Then, a conductive material is deposited over the substrate
100
to fill the opening
214
and the trench
216
. Next, the conductive layer is planarized to form a dual damascene structure
220
and a metallic line
222
. Conventionally, the conductive material can be aluminum or tungsten with a titanium/titanium nitride composite layer underneath serving as barrier layer/glue layer.
In the alternate method as described in
FIG. 2A through 2E
, when the dielectric layer
204
a
is etched to form the opening
214
b
, an etching stop layer having a lower etching rate than the silicon oxide dielectric layer
204
a
such as silicon nitride must be used to control the depth of trench
216
after etching. However, silicon nitride has a dielectric constant higher than silicon oxide and can lead to a higher parasitic capacitance. Moreover, a silicon nitride layer can create internal stress large enough to cause cracks and peeling at the interface between the dielectric layer and the silicon nitride layer. In some cases, the use of high temperature in subsequent processing operations may give rise to serious distortion of the substrate
200
that may affect photolithographic processing operations.
Furthermore, the opening
214
of a dual damascene structure has an upper opening
214
a
and a lower opening
214
b
, and that the profile of the lower opening
214
b
is determined by photoresist layer
212
and the etching stop layer
206
. Therefore, when the photomask is misaligned, size of the lower opening
214
b
is reduced. When conductive material is subsequently deposited into the lower opening
214
b
to form a via plug
220
b
, contacting area between the via plug
220
b
and the first metallic layer
202
will be greatly reduced. Consequently, contact resistan
Huang Yimin
Yew Tri-Rung
Caven Jed W.
Hogan & Hartson LLP
Kubida William J.
Lee Calvin
Smith Matthew
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