Method of forming dual damascene structure

Details Method of forming dual damascene structure Method of forming dual damascene structure

2000-07-07

2002-04-16

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S712000, C438S714000, C438S717000, C438S725000

Reexamination Certificate

active

06372653

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming multi-level interconnect for connecting semiconductor devices. More particularly, the present invention relates to a method of forming a dual damascene structure.
2. Description of Related Art
In the semiconductor industry, much effort is spent in developing semiconductor devices with ever-increasing operating speed. Due to rapid progress in integrated circuit fabrication technologies, resistance of conductive lines and parasitic capacitance resulting from inter-layer dielectric layers have become two main factors affecting the circuit's operating speed. To reduce resistance, low resistance metallic material is often used to form the conductive lines. On the other hand, to reduce parasitic capacitance due to inter-layer dielectric, low dielectric constant material is often used to form the insulation layer between multi-level metallic interconnects.
Conventional metallic interconnects are formed by depositing metal into an opening to form a metal plug and then electrically connecting the metal plug to a conductive line, such as an aluminum line, by forming the conductive line over the substrate. More recently, a dual damascene process has been used to produce high-reliability, low cost metallic lines. In a dual damascene process, material for forming the metallic interconnects is no longer restricted by etching property. Copper, which is one of the principle materials employed in a forming dual damascene structure, is widely adopted due to its intrinsically low electrical resistance. In addition, dielectric layers having low dielectric constants are used inside a dual damascene structure as the level of integration increases.
FIGS. 1A through 1E
are schematic cross-sectional views showing the progression of steps for producing a conventional dual damascene structure. As shown in
FIG. 1A
, a dielectric layer
102
and a silicon nitride layer
104
are formed sequentially over a substrate
100
. A photoresist layer
106
having a via opening
108
is formed therein over the silicon nitride layer
104
.
As shown in
FIG. 1B
, the silicon nitride layer
104
is etched using the photoresist layer as a mask. Hence, the via opening
108
in the photoresist layer
106
is transferred to the silicon nitride layer
104
to form an opening
110
. Another dielectric layer
112
is formed over the substrate
100
, and then another photoresist layer
114
having a trench pattern
116
is formed therein over the dielectric layer
112
.
As shown in
FIG. 1C
, the dielectric layer
112
is etched using the photoresist layer
114
as a mask to form a trench
120
. After the silicon nitride layer
104
is exposed, etching continues down the dielectric layer
102
exposed by the opening
110
to form another via opening
118
.
As shown in
FIG. 1D
, oxygen plasma (O
2
plasma) is used to remove the photoresist layer
114
.
As shown in
FIG. 1E
, metal is deposited to fill the openings
118
and the trench
120
to form a metallic layer
122
. A chemical-mechanical polishing (CMP) operation is next conducted to remove the excess metallic material above the dielectric layer
112
. Hence, a metallic layer
122
that fills the opening
118
and the trench
120
is formed.
As the level of integration of devices in an integrated circuit increases, parasitic capacitance problems caused by an intermediate inter-metal dielectric layer sandwiched between two metallic layers will intensify. To reduce resistance-capacitance time delay due to parasitic capacitance, a low dielectric constant material is often used to form the inter-metal dielectric layer, particularly in a deep sub-micron process.
However, most photoresist layers are produced using high molecular weight compounds, and most low dielectric constant dielectric layers are produced using high molecular weight organic compounds. Hence, when the photoresist layer
114
is removed by oxygen plasma, sidewalls of the via opening
118
and the trench
120
of the low dielectric constant organic dielectric layers
112
and
102
may be damaged. The damaged regions (labeled
124
and
126
in
FIG. 1D
) will likely absorb moisture. The moisture absorbed by the dielectric layers
112
and
102
may poison the metallic material inside the trench
120
and the via opening
118
in the high-temperature metal deposition process.
In addition, the silicon nitride layer
104
is used as an etching stop layer in the process of forming the trench
120
as well as a hard mask layer in the process of forming the via opening
118
. However, the dielectric constant of silicon nitride is rather high, at about seven. Hence, the resulting parasitic capacitance may lead to a high resistance-capacitance delay that affects the operating speed of the highly integrated circuit.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming a dual damascene structure capable of preventing moisture absorption by a low dielectric constant dielectric layer during photoresist removal. Hence, subsequent via poisoning or metallic line poisoning by water is prevented.
A second object of this invention is to provide a method of forming a dual damascene structure capable of reducing the parasitic capacitance and increasing the operating speed of an integrated circuit device.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a dual damascene structure. A first organic low dielectric constant dielectric layer, a heat diffusion layer and a second organic low dielectric constant dielectric layer are formed sequentially over a substrate. A first mask layer having a via opening pattern and a second mask layer having a trench pattern are formed sequentially over the second organic. The second organic low dielectric constant dielectric layer exposed by the via opening pattern is etched using the first mask layer as a hard mask layer. Hence, the via opening pattern on the first mask layer is transferred to the second organic low dielectric constant dielectric layer. The heat diffusion layer exposed by the first mask layer and the via opening in the trench region is removed using the second mask layer and the second organic low dielectric constant dielectric layer as a mask. Hence, the trench pattern and the via opening pattern are transferred to the first mask layer and the heat diffusion layer, respectively. The second organic low dielectric constant dielectric layer within the trench region and the first organic low dielectric constant dielectric layer within the via opening are etched using the second mask layer and the heat diffusion layer as a hard mask. Ultimately, the trench and via opening of a dual damascene structure are formed in the second and first organic low dielectric constant dielectric layers, respectively. Metal is deposited into the trench and the via opening. Then chemical-mechanical polishing is conducted to remove excess material from the metallic layer.
In the process of forming the dual damascene structure, a first photoresist layer and a second photoresist layer are used for transferring the trench pattern and the via opening pattern, respectively. The first photoresist layer is the first mask layer that contains the via opening pattern, and the second photoresist layer is the second mask layer that contains the trench pattern.
After the trench pattern on the first photoresist layer is transferred to the second mask layer, the first photoresist layer is removed by oxygen plasma. Since the second organic low dielectric constant dielectric layer is covered by the first mask layer, the surface of the dielectric layer is spared from plasma damages. Consequently, the removal of the first photoresist layer has no effect whatsoever on the final dual damascene structure.
Similarly, after the via opening pattern on the second photoresist layer is transferred to the first mask layer, the second photoresi

Affiliated with

Also associated with

Rating

Method of forming dual damascene structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming dual damascene structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming dual damascene structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2830740