Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-08-20
1999-12-28
Tsai, Jey
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438620, 438624, 438634, 438637, 438638, 438640, 438644, 438654, 438666, 438672, H01L 214763
Patent
active
060081147
ABSTRACT:
A method of forming a dual damascene structure includes providing a substrate having a metallic layer already formed thereon, and then forming a dielectric layer having a top-wide/bottom-narrow opening over the substrate to expose a portion of the metallic layer. Next, the metallic layer is over-etched by applying etchant through the opening to form a groove in the metallic layer so that additional metallic layer surface is exposed. Thereafter, a glue layer is formed over the opening and the groove surface. If the glue layer is a metal, a high-temperature operation is carried out to form a low resistance alloy at the junction between the metallic layer and the glue layer. Consequently, ohmic contact area and reliability of the device are increased. Finally, conventional processes are used to deposit metal into the opening followed by the planarization of the newly deposited metallic layer.
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Gurley Lynne A.
Tsai Jey
United Microelectronics Corp.
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