Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-15
2004-06-01
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S637000, C438S700000, C438S702000
Reexamination Certificate
active
06743713
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to methods of forming dual damascene patterns and more particularly to methods of forming dual damascene patterns, without the use of etch stop layers, using dual bottom anti-reflective coating (BARC) films.
(2) Description of the Prior Art
Damascene is the practice of creating metal inlay patterns first developed by ancient artisans of Damascus, hence the word damascene. Single damascene and dual damascene patterns are essential today in the fabrication of metal wiring in semiconductor devices and integrated circuits. Dual damascene in particular offers a cost-effective method of forming copper interconnects since copper is hard to etch by a plasma process due to non-volatility of many of its reaction products. Damascene process as practiced today simply consists of etching a wiring trench in a dielectric film followed by filling the trench with metal such as aluminum or copper and then removing the excess metal by a planarizing process Dual damascene involves a second level, wherein a series of via holes are etched and filled by metal in addition to the trench.
Several methods of forming dual damascene patterns have been described in the prior art, and in particular three methods are described: self-aligned, trench-first, and via-first. Self-aligned method has already via patterned and embedded in an intermediate layer. Via hole and trench are etched at the same time. However, this method requires a thick intermediate layer as a trench etch stopper and requires precise alignment accuracy during lithography. Trench-first method is not a very manufacturable process since it requires a thick photo-resist to be able to etch via pattern through an already etched wiring trench; and it is hard to develop a via pattern in thick resist. Via-fist has two approaches: with and without an etch stop layer. In the via-first without an etch stop layer, via is etched first and the trench second. However, trench etch has to be stopped somewhere in the middle of the dielectric. This is practical only if the etch rate uniformities are very good. Secondly, it may be difficult to remove all the photo-resist within via.
In the via-first with an intermediate etch-stop layer, most of the above problems are resolved, while creating a new one. The silicon nitride that is used as an etch stop layer, having a high dielectric constant, is left in place in the structure and increases the overall capacitance when a low-k material is used as the inter-level dielectric. Circuit performance in terms of speed (RC delay) is degraded as a result. All these methods while offering certain advantages also suffer from problems unique to each method.
Two factors are important in fabricating via-first dual damascene structures, particularly when an intermediate etch stop layer is not used: i) via bottom needs to be protected from punch through during trench etch and ii) via edges at the top need to be protected from eroding during trench etch. Anti-reflection coating (ARC) materials have been used in prior art to overcome these problems with only partial success. While conformal ARCs and BARCs alone protect via edges, they cannot prevent punch-through of via bottom, particularly when etch selectivity to the underlying layer is not high enough. Planarizing ARCs and BARCs alone, on the other hand, protect the via-bottom but cannot protect the via-edges due to poor step coverage of the coating around the edges.
Some of these methods and associated problems with each method are described in a paper,
Making the Move to Dual Damascene Processing
, published in Semiconductor International, p. 79, August 1997 and in a paper,
Organic BARC Process Evaluation for Via First Dual Damascene Patterning
, in SPIE Microlithography, February 2001.
U.S. Pat. No. 6,228,760B1 describes a method of covering micro-scratches that are produced in a dielectric layer after chemical mechanical polishing, of a metal interconnect film in a via plug structure. A protective layer of dielectric anti-reflection coating (DARC) or SiON layer is deposited to cover the micro-scratches. To form the metal interconnect pattern, opening is etched in the protective layer and in the dielectric layer. The pattern is then filled with the conductive layer and chemical-mechanically polished to remove the excess conductor layer. The protective layer also serves as a polish stop to prevent new scratches being formed in the dielectric layer.
U.S. Pat. No. 6,251,7741B1 describes a method of manufacturing a semiconductor device to form a metal interconnect in a via-first type of dual damascene structure on a lower metal pattern without damaging the lower wiring layer. According to the process, a first silicon nitride film, a first silicon oxide film, a second silicon nitride film, and a second silicon oxide film are sequentially deposited on the lower wiring layer. A via hole is etched above the wiring layer, passing through the top two layers. A photo resist is filled within via so as to cover the internal wall surface and BARC material is then deposited over the oxide. BARC film is used to enhance the performance of the lithographic step in defining the trench mask pattern with superior dimensional accuracy. Wiring trench is then etched while the resist in via protects the first silicon nitride film from punch-through. Via steps, however, are not adequately protected.
U.S. Pat. No. 6,306,732B1 describes an apparatus and method for improving electro-migration reliability and resistance of a single or dual damascene via by using an imperfect barrier film at the bottom of the via and a strong barrier formed at all other portions of the via. The imperfect barrier allows for metal atoms to flow through when electro-migration force pushes the metal atoms against the barrier film.
U.S. Pat. No. 6,265,294 describes a fabrication method to reduce the amount of discoloration on inter-level dielectric layers due to anti-reflection coatings (ARCs). This patent uses a barrier layer such as silicon nitride to prevent the ARC from coming in contact with the inter-level dielectric film. The ARCs used are of the inorganic type such as silicon oxy-nitride (SiON).
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to describe a method to form a via-first dual damascene wiring pattern, without punch-through of the via-bottom or erosion of via-corners.
It is yet another object of the invention to describe a method of forming a via-first dual damascene wiring pattern, using two layers of two different types of bottom anti-reflective coating films within the via prior to etching of the wiring trench.
Yet another object of this invention is to describe a method of forming a via-first dual damascene pattern, without the use of an intermediate etch stop layer.
In accordance with these objectives, a method is described to form a via-first dual damascene structure, in the absence of an etch stop layer, without punch-through of via bottom or eroding via corners during etching of wiring trench. Over metal wiring protected by a barrier film, an inter-level dielectric film is deposited and via is etched in the dielectric film stopping on the barrier layer. Via walls and surfaces are then conformally coated with a first type of BARC film, which protects via step during etching. Via pattern is further filled, partially or fully, with a second, planarizing type of BARC material. Wiring trench pattern is then formed using a trench resist mask and plasma etching process. The two BARC films together protect both the via-bottom and via-corners during trench etching. Stripping the mask and BARC films at the same time and cleaning any of the organic BARC residues in the pattern complete the process.
REFERENCES:
patent: 6228760 (2001-05-01), Yu et al.
patent: 6251774 (2001-06-01), Harada et al.
patent: 6265294 (2001-07-01), Park et al.
patent: 6306732 (2001-10-01), Brown
patent: 6309955 (2001-10-01), Subramanian et al.
patent: 6380096 (2002-04-01), Hung et al.
patent: 6391761 (2002-05
Bliznetsov Vladimir N.
Mukherjee-Roy Moitreyee
Ackerman Stephen B.
Chen Jack
Institute of Microelectronics
Pham Thanhha
Saile George O.
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