Method of forming dual damascene pattern in semiconductor...

Details Method of forming dual damascene pattern in semiconductor... Method of forming dual damascene pattern in semiconductor...

2005-01-11

2005-01-11

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S638000, C438S700000, C438S702000, C438S703000, C438S736000, C438S948000, C438S949000, C438S950000, C438S952000

Reexamination Certificate

active

06841465

ABSTRACT:
Disclosed is a method of forming the dual damascene pattern in the semiconductor device. After forming the trench, a photoresist pattern in which a via hole region is defined is formed by exposure and development processes in a state that a photoresist is thinly coated, in a dual damascene process for first forming the trench than a via hole. Therefore, the present invention can prevent degradation of resolution due to a thickness of a photoresist pattern in a trench region and improve reliability of the entire process by simultaneously smoothly performing an etching process even with a thin photoresist pattern due to a good etching tolerance property.

REFERENCES:
patent: 5403435 (1995-04-01), Cathey et al.
patent: 6020255 (2000-02-01), Tsai et al.
patent: 6521542 (2003-02-01), Armacost et al.
patent: 6602794 (2003-08-01), Kye
patent: 6720256 (2004-04-01), Wu et al.
patent: 20020084257 (2002-07-01), Bjorkman et al.

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