Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2003-09-17
2004-09-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S164000, C438S311000, C438S337000
Reexamination Certificate
active
06787404
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating double-gated semiconductor-on-insulator-on-insulator (SOI) transistors.
BACKGROUND OF THE INVENTION
Double-gated transistors offer greater performance compared to conventional planar transistors. However, a problem has been how to fabricate such double-gated transistors. Current techniques being examined today include epitaxial growth to form the channel after gate oxidation and fin field effect transistors (FET) (so named “fin” as its appearance is that of a fish's fin). However, both of these techniques have significant limitations.
U.S. Pat. No. 6,451,656 B1 to Yu et al. describes a double-gate transistor on semiconductor-on-insulator (SOI).
U.S. Pat. No. 6,413,802 B1 to Hu et al. describes a double-gate FinFFET on semiconductor-on-insulator (SOI).
U.S. Pat. No. 6,365,465 B1 to Chan et al. also describes a process for a double-gate MOSFET on semiconductor-on-insulator (SOI).
U.S. Pat. No. 6,396,108 B1 to Krivokapic et al. describes a process for a double-gate MOSFET on semiconductor-on-insulator (SOI).
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide methods of forming double-gated silicon-on-insulator (SOI) transistors having reduced gate to source-drain overlap capacitance.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening. The SOI oxide layer is etched while minimizing the undercut portions of the upper surface of the SOI oxide layer are undercut into the SOI oxide layer to form a minimal undercut. The minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI silicon layer. A conformal oxide layer is formed around the channel portion of the patterned SOI silicon layer. A gate is formed within the patterned dummy layer opening. The gate including an upper gate above the patterned SOI silicon layer and a lower gate under the patterned SOI silicon layer. The patterned dummy layer is then removed to form the double-gated transistor.
REFERENCES:
patent: 6365465 (2002-04-01), Chan et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6451656 (2002-09-01), Yu et al.
Jin Da
Lee Yong Meng
Vigar David
Chartered Semiconductor Manufacturing Ltd.
Isaac Stanetta
Niebling John F.
Pike Rosemary L. S.
Saile George O.
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