Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-08-24
2001-01-09
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S745000, C438S756000
Reexamination Certificate
active
06171968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a damascene structure. More particularly, the present invention relates to a method of forming a damascene structure having a borderless via or contact opening design.
2. Description of Related Art
In general, there are two methods of forming metallic lines. In the first method, a metallic layer is deposited over interconnects, and then a patterned photoresist layer is formed over the metallic layer. Thereafter, the metallic layer is etched to form the required metallic line, and finally an inter-metal dielectric (IMD) layer is deposited over the metallic line.
In the second method of forming the metallic line, a dielectric layer is first deposited over interconnects, and then a patterned photoresist layer is deposited over the dielectric layer. Thereafter, the dielectric layer is etched to form a trench, and then metallic material is deposited into the trench. Finally, a chemical-mechanical polishing (CMP) method is used to remove excess metallic material over the dielectric layer, thereby forming a damascene structure.
As the number of conductive lines required for interconnecting integrated circuit devices increases, designs having two or more metallic layers are becoming a necessity. In general, an inter-metal dielectric (IMD) layer is formed between neighboring metallic layer for isolation. In the classical method of forming via or contact opening in the dielectric layer, design rules must be followed so that a minimum width must be laid aside as the border that surrounds the via or contact opening. Therefore, if there is any misalignment between the via or contact opening and a conductive line, leakage current from the device can be prevented.
However, as the level of integration for devices continue to increase, devices having line widths of about 0.25 &mgr;m or smaller are common. When dimensions of device are so small, a borderless via or contact opening design must be used. In other words, border area surrounding the via or contact opening are not included in the design. Because there is no border area around the via or contact opening, any misalignment of the trench for forming the conductive line results in reduced contact area between conductive line and the via or contact opening. Consequently, resistance between the conductive line and the via or contact opening will increase, thereby affecting the operational speed of the device. Hence, the quality of the device may drop resulting in the lost of certain functions.
FIGS. 1A
,
1
B,
1
C,
1
D, and
1
E are cross-sectional views showing the progression of manufacturing steps in forming a damascene structure having borderless via or contact opening design according to the conventional method.
First, a planarized substrate structure
100
(devices within the substrate structure
100
are not fully drawn) is provided as shown in FIG.
1
A. The substrate structure
100
has a conductive line
102
. The conductive line
102
can be formed, for example, by first forming a conductive layer (not shown in the figure) over the substrate structure
100
, and then patterning the conductive layer to form the conductive line
102
. Furthermore, the conductive line
102
is connected to a conductive region (also not shown in the figure) somewhere in the substrate structure
100
.
Next, as shown in
FIG. 1B
, a dielectric layer
104
is formed over the substrate structure
100
. For example, a chemical vapor deposition (CVD) method is used to form a silicon oxide layer over the substrate. Then, conventional photolithographic and etching operations are used to form a via opening
105
in the dielectric layer
104
. The via opening
105
exposes a portion of the conductive line
102
.
Next, as shown in
FIG. 1C
, a glue/barrier layer
106
conformal to the via opening
105
is formed over the dielectric layer
104
. The glue/barrier layer
106
serves to increase adhesion between subsequently deposited metallic layer and other material layer. Thereafter, a metallic layer is deposited over the dielectric layer
104
. For example, a chemical vapor deposition method is used to deposited a layer of tungsten that fills the via opening
105
making electrical connection with the conductive line
102
. Subsequently, the tungsten layer is either etched back or planarized using a chemical-mechanical polishing method to remove redundant material above the dielectric layer
104
. Ultimately, a via plug
108
is formed.
Next, as shown in
FIG. 1D
, another dielectric layer
114
is formed over the dielectric layer
104
. For example, a chemical vapor deposition (CVD) method is used to deposit a silicon oxide layer. Then, conventional photolithographic and etching operations are used to form a trench
115
in the dielectric layer. The trench
115
exposes a portion of the via plug
108
. Due to misalignment of the trench
115
, a subsequently formed conductive line in the trench
115
will have a smaller contact area with the via plug
108
. Consequently, resistance between the conductive line and the via plug
108
will greatly increase.
Next, as shown in
FIG. 1E
, a conductive layer
112
is deposited over the dielectric layer
114
. For example, metallic material such as copper, aluminum, or aluminum-copper alloy is deposited into the trench
115
. Then, a chemical-mechanical polishing (CMP) operation is carried out to remove excess conductive layer above the dielectric layer
114
. Therefore, a conductive line
112
having electrical connection with the via plug
108
is formed. However, contact area between the conductive line
112
and the via plug
108
is greatly reduced due to the misaligned trench
115
. Hence, there is a high contact resistance between the conductive line
112
and the via plug
108
.
In light of the foregoing, there is a need to improve the method of forming a damascene structure that has a borderless via or contact opening design.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of forming a damascene structure having a borderless via design such that despite any misalignment between the conductive line and the via plug, contact area between the conductive line and the via plug can be maintained, and hence contact resistance between the conductive line and the via plug can be kept at a minimum.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming damascene structure having a borderless via design. The method comprises the steps of forming a first conductive line above a substrate structure, and then forming a first dielectric layer having a via opening that exposes a portion of the first conductive layer. Thereafter, a metallic plug electrically connected to the first conductive line is formed in the via opening. Next, an insulating layer and a second dielectric layer are sequentially formed over the first dielectric layer. Subsequently, the second dielectric and the insulating layer are patterned to form a trench. Then, portions of the insulating layer at the bottom of the trench are removed to from cavity regions. Finally, a second conductive line that connects electrically with the metallic plug is formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5891799 (1999-04-01), Tsui
patent: 5933761 (1999-08-01), Lee
Chen Kin-Chan
Kunemund Robert
United Microelectronics Corp.
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