Metal fusion bonding – Process – Preplacing solid filler
Reexamination Certificate
2000-10-23
2002-05-21
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
Preplacing solid filler
C228S248500
Reexamination Certificate
active
06390356
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a method of forming cylindrical bumps on a substrate for integrated circuits, which comprises the step of covering the substrate with a screening material, forming openings in the screening material to align with the copper circuits of the substrate, filling the openings with pure copper or high melting point metal to form cylindrical bumps, and then forming a layer of solder alloy on the top of each of the cylindrical bumps.
2. Description of the Prior Art
In the conventional flip chip technological process for connecting a die
2
′ to a substrate
1
′ (see
FIGS. 1
a
and
1
b
), it is necessary to form under-bump-metallurgy (UBM) layers
21
′ from the input/output (I/O) of the die
2
′ and bumps
22
′ of solder alloy on the under-bump-metallurgy layers
21
′, and then turn over the die
2
′ to engage the substrate
1
′ (copper circuits
12
′ have already been formed on the board
11
′ of the substrate
1
′). Thereafter, a underfill
3
′ is filled between the substrate
1
′ and the die
2
′.
However, the bumps
22
′ made of solder alloy will be melted in a process at 100~350 degrees centigrade so that the gravitational force will lower the position of the die
2
′ thus reducing the distance between the bumps
22
′ of the die
2
′ and the substrate
1
and therefore increasing the difficulty in filling the underfill
3
′. Hence, this method always results in some cylindrical bumps being defective, the numbers of which cannot be reduced.
Therefore, it is an object of the present invention to provide a method of forming cylindrical bumps on a substrate for integrated circuits which can obviate and mitigate the above-mentioned drawbacks.
SUMMARY OF THE INVENTION
This invention is related to a method of forming cylindrical bumps on a substrate for integrated circuits, which comprises the step of covering the substrate with a screening material, forming openings in the screening material to align with the copper circuits of the substrate, filling the openings with pure copper or high melting point metal to form cylindrical bumps, and then forming a layer of solder alloy on the top of each of the cylindrical bumps.
It is the primary object of the present invention to provide a method of forming bumps on a substrate for integrated circuits which includes the steps of increasing the thickness of the copper circuits and then electroplating a layer of solder alloy on the copper circuits so that the solder alloy will be melted but the copper or high melting point metal will not be melted in operation at temperatures between 100~350 degrees cenfigrade, thereby enabling the distance between the die and the substrate to be accurately controlled and therefore facilitating the filling of underfill.
It is another object of the present invention to provide a method of forming cylindrical bumps on a substrate for integrated circuits wherein the bumps are formed on the substrate instead of the die so that even if there is something wrong with the process of forming bumps on the substrate, the die has no need to be discarded, thereby decreasing the manufacturing cost.
It is a further object of the present invention to provide a method of forming cylindrical bumps on a substrate for integrated circuits which only requires the die to be coated with a under-bump-metallurgy layer rather than a under-bump-metallurgy layer and formation of bumps on the under-bump metallurgy layer as required by the conventional method, thereby reducing the time and cost of manufacturing dies.
The foregoing objects and summary provide only a brief introduction to the present invention. To fully appreciate these and other objects of the present invention as well as the invention itself, all of which will become apparent to those skilled in the art, the following detailed description of the invention and the claims should be read in conjunction with the accompanying drawings. Throughout the specification and drawings identical reference numerals refer to identical or similar parts. Many other advantages and features of the present invention will become manifest to those versed in the art upon making reference to the detailed description and the accompanying sheets of drawings in which a preferred structural embodiment incorporating the principles of the present invention is shown by way of illustrative example.
REFERENCES:
patent: 3697828 (1972-10-01), Oakes
patent: 5759737 (1998-06-01), Feilchenfeld et al.
patent: 5775569 (1998-07-01), Berger et al.
patent: 5860585 (1999-01-01), Rutledge et al.
patent: 5868304 (1999-02-01), Brofman et al.
patent: 5872051 (1999-02-01), Fallon et al.
patent: 5902686 (1999-05-01), Mis
patent: 5984166 (1999-11-01), Holzmann
patent: 6158650 (2000-12-01), Holzmann
Chang Chung Ming
Chang Hsuan Jui
Chen Hui-Pin
Chiang Hua Wen
Chuang Yung-Cheng
A & J
Dunn Tom
Orient Semiconductor Electronics Limited
Pittman Zidia
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