Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-05-30
2000-10-10
Chang, Joni
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
257751, H01L 2348
Patent
active
061301612
ABSTRACT:
A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with halfnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper intersititial positions.
REFERENCES:
patent: 4007039 (1977-02-01), Shapiro et al.
patent: 4017890 (1977-04-01), Howard et al.
patent: 4154874 (1979-05-01), Howard et al.
patent: 4379832 (1983-04-01), Dalal et al.
patent: 4406858 (1983-09-01), Woodford et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4872048 (1989-10-01), Akutsu et al.
patent: 4985750 (1991-01-01), Hoshino
patent: 5187300 (1993-02-01), Norman
patent: 5252516 (1993-10-01), Nguyen et al.
patent: 5300813 (1994-04-01), Joshi et al.
patent: 5312509 (1994-05-01), Eschbach
patent: 5322712 (1994-06-01), Norman et al.
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5403779 (1995-04-01), Joshi et al.
patent: 5414301 (1995-05-01), Thomas
patent: 5426330 (1995-06-01), Joshi et al.
patent: 5434451 (1995-07-01), Dalal et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5527739 (1996-06-01), Parrillo et al.
patent: 5539256 (1996-07-01), Mikagi
patent: 5565707 (1996-10-01), Colgan et al.
patent: 5656860 (1997-08-01), Lee
IBM Technical Disclosure Bulletin, Optimum Metal Line Structures for Memory Array and Support Circuits, vol. 30, No. 12; May, 1988.
VLSI Multilevel Interconnection Conference (VMIC) ,Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices, by Luther et al.; pp. 15-21, 1993.
Ashley Leon
Dalal Hormazdyar M.
Nguyen Du Binh
Rathore Hazara S.
Smith Richard G.
Ahsan Aziz M.
Chang Joni
International Business Machines - Corporation
Sulsky Martin
Ziegler, Jr. Geza C.
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