Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2000-11-11
2002-09-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S978000, C438S640000, C430S312000, C430S349000, C430S394000, C430S494000
Reexamination Certificate
active
06448183
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a manufacturing process for a semiconductor element, and more particularly, to a method for forming a contact portion used in electrically connecting upper and lower conductive layers, which are electrically separated by an insulation layer.
(b) Description of the Related Art
In a semiconductor integrated circuit, there are formed, within an area limited according to the level of increased density, contact holes for connecting a metal wiring layer with a gate, source and drain formed on a semiconductor substrate, and via-holes for making connections between metal wiring layers.
In particular, in multi-layer wiring technology, since a space through which wires pass through between semiconductor elements is of no consequence, it is possible to minimize the size of the semiconductor chip. However, since the multi-layer wiring technology is applied by repeating a layer growing process, defects such as the disconnection of wires can result on a surface. Step coverage or contact defects resulting from an irregular surface at areas where wires cross are particularly problematic.
Further, after contact holes and via-holes are formed, and a metal barrier is deposited, when tungsten is adhered for covering the via-holes, problems such as voids being formed in the holes result.
Accordingly, in recent times, in the process of forming the contact holes and via-holes of the semiconductor element, in the case of adhering a barrier metal in the contact holes or via-holes in order to improve step coverage and prevent the formation of voids, an upper portion of the contact holes or via-holes are made slanted using a sputter etch process that employs argon gas. Subsequently, tungsten is used to cover the holes.
However, in such a method, argon sputter etching of an upper part of the contact holes does not form a smooth slant all the way to a lower portion of the contact holes. Accordingly, the step coverage problem can not be fully solved and an evenness of the semiconductor substrate is not realized. Further, the addition of the argon sputter etching process increases overall manufacturing costs.
SUMMARY OF THE INVENTION
The present invention has been made in an effort to solve the above problems.
It is an object of the present invention to provide a method for forming a contact portion used in electrically connecting upper and lower conductive layers in which, when forming contact holes for connecting a gate, source and drain with a metal wiring layer, and via-holes for making a connection between metal wiring layers, step coverage is effectively improved with no increase in manufacturing costs.
To achieve the above object and others, the present invention provides a method for forming a contact portion of a semiconductor element comprising the steps of: depositing an insulation layer on a lower thin film on which there is formed a semiconductor element electrode or a metal wiring pattern, and then providing a planar top surface of the insulation layer; forming a photosensitive film pattern having a contact or via hole pattern in which inner walls of the contact holes or via holes smoothly curve downward to reach an upper surface of the insulation layer; dry-etching the insulation layer using a mask following the photosensitive film pattern to form contact holes or via holes; removing the photosensitive film pattern, then depositing a barrier metal and tungsten to fill the contact holes or the via holes; and performing a chemical mechanical polishing process to remove the barrier metal and the tungsten from the upper surface of the semiconductor element until the insulation layer is exposed and a flat surface is realized.
According to a feature of the present invention, the step of forming the photosensitive film pattern having a contact or via hole pattern in which the inner walls of the contact holes or via holes smoothly curve downward comprises the steps of depositing a photosensitive film on an upper surface of the insulation layer and developing the photosensitive film through a light exposure process using a mask on which there is formed a contact hole or via-hole pattern, thereby forming a photosensitive film pattern in which inner walls of the photosensitive film pattern are stepped; and hard baking the photosensitive film pattern fabricated in a stepped formation such that the stepped formation is smoothed.
According to another feature of the present invention, in order to form the stepped pattern of the inner walls of the photosensitive film pattern, a temperature is sequentially or continuously varied during the depositing of the photosensitive film.
According to yet another feature of the present invention, the temperature is varied by altering a temperature of a sub-plate used to support a wafer.
According to still yet another feature of the present invention, the temperature is varied using a heater affixed to the outside of a nozzle, the nozzle being used for depositing the photosensitive film.
According to still yet another feature of the present invention, in order to form the stepped pattern of the inner walls of the photosensitive film pattern, a layered structure using photosensitive films of differing sensitivities is used during the depositing of the photosensitive film.
According to still yet another feature of the present invention, in order to form the stepped pattern of the inner walls of the photosensitive film pattern, an exposure energy is sequentially or continuously varied during the exposing of the photosensitive film.
REFERENCES:
patent: 5359101 (1994-10-01), Woods et al.
patent: 5882999 (1999-03-01), Anderson et al.
patent: 62137831 (1987-06-01), None
Anam Semiconductor Inc.
Pham Thanh
Skjerven Morrill LLP
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