Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-02
2001-07-17
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06261948
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to a method of forming contact openings and to electronic components formed from the same and other methods.
BACKGROUND OF THE INVENTION
As various electronic components such as DRAMS have increased in memory cell density, designers face a continuous challenge to provide contact openings to predetermined node locations, and to the top surface of conductive lines.
Heretofore, so-called self-aligned contact openings are provided to node locations which are adjacent to wordlines, by first encapsulating the wordline in nitride spacers, and providing a nitride cap thereover. Once this is achieved, a silicon dioxide layer in the form of BPSG, is provided over the encapsulated wordline. Following the provision of the layer of BPSG, the contact opening is etched. In view of perceived shortcomings in the prior art techniques, the patterning and etching of the contact openings through the layer of BPSG to the node location, can be somewhat misaligned. To address this problem, an etching chemistry is provided which is selective to nitride and therefore the etching will stop on the nitride material which encapsulates the wordline.
In addition to the foregoing, the fabrication of certain electronic components may require that contact openings be made to both the top surface of the respective wordlines and to substrate areas adjacent thereto. To make electrical contact to the top surface of wordlines, the prior art techniques have typically included separate photo patterning, and etching steps. The present method provides a convenient means by which contact openings to the top surface of the wordline, and adjacent node location can be provided in a single photo masking and etching step.
REFERENCES:
patent: 4281448 (1981-08-01), Barry et al.
patent: 4936928 (1990-06-01), Shaw et al.
patent: 5162890 (1992-11-01), Butler
patent: 5166096 (1992-11-01), Cote et al.
patent: 5173752 (1992-12-01), Motonami et al.
patent: 5206187 (1993-04-01), Doan et al.
patent: 5243219 (1993-09-01), Katayama
patent: 5272367 (1993-12-01), Dennison et al.
patent: 5317193 (1994-05-01), Watanabe
patent: 5444003 (1995-08-01), Wang et al.
patent: 5510648 (1996-04-01), Davies et al.
patent: 5547892 (1996-08-01), Wuu et al.
patent: 5552620 (1996-09-01), Lu et al.
patent: 5576243 (1996-11-01), Wuu et al.
patent: 5591662 (1997-01-01), Zambrano
patent: 5612240 (1997-03-01), Chang
patent: 5652174 (1997-07-01), Wuu et al.
patent: 5668021 (1997-09-01), Subramanian et al.
patent: 5686331 (1997-11-01), Song
patent: 5707883 (1998-01-01), Tabara
patent: 5710450 (1998-01-01), Chau et al.
patent: 5731610 (1998-03-01), Rhodes
patent: 5736441 (1998-04-01), Chen
patent: 5747359 (1998-05-01), Yuan et al.
patent: 5763321 (1998-06-01), Ohshima et al.
patent: 5811350 (1998-09-01), Dennison
patent: 5827770 (1998-10-01), Rhodes et al.
patent: 5858832 (1999-01-01), Pan
patent: 5864155 (1999-01-01), Melzner
patent: 5866927 (1999-02-01), Cho et al.
patent: 5874359 (1999-02-01), Liaw et al.
patent: 5885890 (1999-03-01), Dennison
patent: 5891780 (1999-04-01), Hasegawa et al.
patent: 5895269 (1999-04-01), Wang et al.
patent: 5897350 (1999-04-01), Lee et al.
patent: 5899712 (1999-05-01), Choi et al.
patent: 5912492 (1999-06-01), Chang et al.
patent: 5930618 (1999-07-01), Sun et al.
patent: 5946578 (1999-08-01), Fujii
patent: 5960318 (1999-09-01), Peschke et al.
patent: 5970360 (1999-10-01), Cheng et al.
patent: 6093609 (2000-07-01), Chuang
patent: 6097103 (2000-08-01), Ishigaki
patent: 6133103 (2000-10-01), Lee et al.
Wolf, S., “Silicon Processing for the VLSI Era”, vol. 3: The Submicron MOSFET, Lattice Press 1995, pp. 136-138, 232-234, 634-646.
Gray, Paul R. et al., “Analysis and Design of Analog Integrated Circuits,” Third Edition, 1993, John Wiley and Sons, p. 169—specifically the 2ndparagraph.
U.S. application No. 08/399,844, Rhodes, filed Mar. 7, 1995.
Shenai, K., “A high-density, self-aligned power MOSFET structure fabricated using sacrificial spacer technology” Electron Devices, IEEE Transaction on Electron Devices, vol. 39 Issue 5, May 1992, pps 1252-1255.
Micro)n Technology, Inc.
Nguyen Tuan H.
Thompson Craig
Wells St. John Roberts Gregory & Matkin
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