Method of forming contact for semiconductor device

Details Method of forming contact for semiconductor device Method of forming contact for semiconductor device

1999-08-16

2001-07-03

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S724000, C438S743000

Reexamination Certificate

active

06255224

ABSTRACT:

This application relies for priority upon Korean Patent Application No.98-34716, filed on Aug. 26, 1998, the content of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a method of forming a contact for a dynamic random access memory (DRAM) device.
BACKGROUND OF THE INVENTION
As DRAM devices are designed with greater densities, the photo process used to make them becomes increasingly difficult, since the design rule must be continually reduced. For example, in a 256 Mbit DRAM, the design rule has been reduced to less than 0.2 micrometers. In order to solve this problem, a photoresist (PR) flow process has been adopted. In the PR flow process, however, the PR flow amounts vary depending upon the design sizes. As a result, there are difficulties in applying this process.
FIGS. 1A
to
1
D illustrate the conventional method for forming contacts in a semiconductor device.
Referring to
FIG. 1A
, a device isolating region
12
is initially formed to define an active region in a semiconductor substrate
10
. A cell transistor is then formed over the semiconductor substrate
10
. As is generally well known, in forming the cell transistor, a gate electrode is formed by sequentially stacking a gate oxide layer (not shown), a polysilicon layer
14
a
, and a silicide layer
14
b
. Furthermore, a source/drain region (not shown) is formed in the semiconductor substrate
10
along both sides of the gate electrode layers
14
a
and
14
b
. Then, in order to insulate the gate electrode layers
14
a
and
14
b
, a gate mask
14
c
is formed over the silicide layer
14
b
to complete the gate electrode stack
14
, and a nitride spacer
15
is formed on side walls of the polysilicon layer
14
a
and the silicide layer
14
b.
A first inter-layer insulating layer
16
is then formed over the semiconductor substrate
10
, covering the gate electrode stack
14
. The first inter-layer insulating layer
16
may be, for example, a BPSG layer. Then, the first inter-layer insulating layer
16
is flattened using a BPSG flow process and a chemical mechanical polishing (CMP) process. The first inter-layer insulating layer
16
is then etched using a contact hole forming mask
18
until the semiconductor substrate
10
of the cell region is exposed, thereby forming a self-aligned contact pad forming contact holes
20
.
Referring to
FIG. 1B
, a polysilicon layer (not shown) is formed over the first inter-layer insulating layer
16
, filling the contact holes
20
. Then the polysilicon layer is etched using an etch-back process or a CMP process, and thus self-aligned contact pads
22
a
and
22
b
, i.e., a DC pad
22
a
and a BC pad
22
b
, are formed. The DC pad
22
a
and the BC pad
22
b
are each electrically connected to the semiconductor substrate
10
.
Then, a second inter-layer insulating layer
24
is formed over the first inter-layer insulating layer
16
, covering the self-aligned pads
22
a
and
22
b
. The second inter-layer insulating layer may be, for example, a PE-TEOS layer. The second inter-layer insulating layer
24
is then etched, using a first contact hole forming mask
26
, until the surfaces of the cell region and the DC pad
22
a
are exposed. In this manner, a bit line DC contact hole
27
is formed.
As shown in
FIG. 1C
, the first contact hole forming mask
26
is then removed. After that, the second and first inter-layer insulating layers
24
and
16
are sequentially etched by using a second contact hole forming mask
28
, until the surface of the semiconductor substrate
10
in the core region is exposed, thereby forming a core DC contact hole
29
.
As described above, as DRAM devices achieve higher densities, it becomes very difficult to simultaneously form DCs both at the cell array region and in the core/peripheral region since two different fine patterns are required for the cell array region and core/peripheral region. Therefore, the photo process for DC formation cannot be applied simultaneously to both the cell array region and the core/peripheral region.
Referring to
FIG. 1D
, the second contact hole forming mask
28
is removed. Then, a polysilicon layer
30
is formed over the second inter-layer insulating layer
24
, filling both the bit line DC contact hole
27
and the core DC contact hole
29
. The polysilicon layer
30
is then flattened in such a manner that some thickness of the second inter-layer insulating layer
24
remains. Then, a bit line forming tungsten silicide layer
32
is formed over the polysilicon layer
30
.
Finally, the silicide layer
32
and the polysilicon layer
30
are sequentially etched using a bit line forming mask (not shown). As a result, bit lines are formed that are electrically connected through the direct contacts of the cell region and the core region to the DC pad
22
a
and to the semiconductor substrate
10
.
The above-mentioned method uses two photolithography processes for the formation of DCs both at the cell array region and in the core/peripheral region, resulting in process complexity and high manufacturing cost. Accordingly, there is a need of a method that can form a direct contact at the cell array region and at the peripheral region using a simple process having a low cost.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above described disadvantages of the conventional technique.
Therefore it is an object of the present invention to provide a method of forming a contact for a semiconductor memory device, in which when forming the direct contacts in the cell and core regions, the process can be simplified sufficiently to save on manufacturing costs.
The present invention provides a method for forming contacts in a semiconductor substrate. In this method, first and second contact pads are formed over a semiconductor substrate in such a manner that top surfaces of the contact pads are lower in level as compared to a top surface of the first insulating layer formed over them. Then a second insulating layer that exhibits a poor step coverage is formed over the first insulating layer. The second insulating layer is then etched until the surfaces of the first and second contact pads are exposed. Then, a first conductive layer is formed over the semiconductor substrate, and the first conductive layer is flattened such that it leaves a partial thickness of the second insulating layer. A second conductive layer is then formed over the first conductive layer, and the second and first conductive layers are sequentially etched, using a bit line forming mask, to form a bit line. Under this condition, the first conductive layer, over the first self-aligned contact pad, is over-etched to form an electrical insulation from the bit line. In this method, when forming the direct contacts (DCs) of a cell region and a core region, the photo process for forming the direct contact of the cell region or forming the buried contact and direct contact of the cell region, and the photo process for forming the direct contact of the core region can be skipped to simplify the formation process, thereby saving the manufacturing cost.
In achieving the above object, the method for forming a contact in a semiconductor memory device according to the present invention includes forming a transistor over a semiconductor substrate, forming a first insulating layer over the semiconductor substrate and the transistor, forming first and second contact pads in the insulating layer, top surfaces of the contact pads being lower in level as compared to a top surface of the first insulating layer, forming a second insulating layer over the first insulating layer, the second insulating layer exhibiting a poor step coverage, etching the second insulating layer until surfaces of the first and second contact pads are exposed, forming a first conductive layer over the semiconductor substrate, and the first and second insulating layers, and forming a second conductive layer over the flattened first conductive layer.
The meth

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