Method of forming connections with low dielectric insulating...

Details Method of forming connections with low dielectric insulating... Method of forming connections with low dielectric insulating...

2000-08-28

2003-01-14

Powell, William A. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C216S067000, C216S079000, C438S723000, C438S734000, C438S740000

Reexamination Certificate

active

06506680

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor manufacturing method, and more particularly to a method of forming dual-damascene metallic interconnections with low dielectric constant insulating layers.
2. Description of the Related Art
As the semiconductor device packing density increases, performance in speed tends to degrade. Degradation can be caused by increased resistance and parasitic capacitance of the metal interconnections. In particular, devices made according to design rules of 0.25 &mgr;m or less suffer greater speed degradation due to the resistance and capacitance of the interconnections. Even a reduction of gate length does not significantly improve speed in this situation. One proposed solution is to use copper (Cu), instead of aluminum (Al) for metallization since the electrical resistance of Cu is about one third of that of Al.
In devices wherein the metal interconnection is structured in a multilevel fashion, resulting in an increased aspect ratio of contact holes, the device further suffers from non-flatness (non-uniformity or surface irregularities), bad step coverage, residual metal short-circuits, low yield rate, degraded reliability, etc. It is, however, known to use a damascene process to resolve some of these problems. The damascene process comprises the steps of etching an insulating layer to form trenches, depositing a metal layer in and over the trenches, and removing the excessive metal layer by chemical mechanical polishing (CMP), so that the metal interconnections are arranged in a line and space pattern embedded in the trenches. A dual damascene process advantageously fills via-holes or contact holes simultaneously during metallization.
FIG. 1
is a cross sectional view illustrating the step of forming a via-hole in a previously formed trench using a dual-damascene process. Referring to
FIG. 1
, a lower metal interconnection layer
10
comprising or consisting of Al, Cu or Al—Cu alloy is deposited on a semiconductor substrate (not shown) covered with an insulating layer. Deposited over the lower metal interconnection layer is an oxide layer that forms an inter-metal dielectric layer (IMD)
12
. The IMD layer
12
is etched by a photolithographic process to form the trench
14
, over which is laid a photoresist pattern
16
to define the contact hole. The IMD
12
layer is etched according to the photoresist pattern
16
to form the contact hole
18
, thereby exposing the lower metal interconnection layer
10
.
Problems encountered in the conventional process include non-uniformity of the trench depth and formation of micro-trenches which appear towards the sidewalls at the bottom of the trench, which is caused by using the time-etching process without selectivity. In addition, as the trench depth is increased, it becomes more difficult to use a photolithographic process to define the contact hole. For example, if the trench depth is 15000Å, and the thickness of the photoresist defining the contact hole is 1 &mgr;m, the thickness of the photoresist in the trench becomes about 2.5 &mgr;m due to the photoresist filling the trench. In such a case, the photoresist in the trench region may not be sufficiently exposed to light during a subsequent exposing step, and the high step between the trench and the other regions causes irregular light reflection, distorting the profile of the contact hole.
To resolve the above problems, a proposed dual damascene process is employed to form first the contact hole before the step of producing the trench and the step of a single-damascene process comprising filling the contact hole and metallization. However, the single-damascene process requires chemical mechanical polishing (CMP) separately for each of the steps of forming the contact-hole plug and metallization. The conventional dual-damascene process is described below.
FIG. 2
illustrates a conventional self-aligned dual damascene (SADD) process where an oxide layer is deposited on a lower metal interconnection layer
20
to form a lower insulating interlayer
22
. Layer
22
is subsequently covered by a nitride layer
24
to serve as an etching stopper layer, which is etched to define the region of the contact hole. Deposited over it is an oxide layer to form an upper insulating interlayer
26
, which is covered by a photoresist pattern
28
to define the trench region. The upper insulating interlayer
26
is etched with high selectivity to the etching stopper layer
24
to form the trench
30
according to the photoresist pattern
28
. Removing the photoresist pattern
28
, the lower insulating interlayer
22
is etched using the etching stopper layer
24
as a mask to form the contact hole
32
, exposing the lower metal interconnection layer
20
.
Although the above-described SADD process achieves uniformity of the trench depth, and prevents micro-trenches from being generated because of etching the trench with high selectivity to the etching stopper layer of nitride, it inevitably increases the parasitic capacitance of the metal interconnections because the nitride layer has a high dielectric constant.
FIG. 3
illustrates a conventional couter-bore dual damascene (CBDD) process, where an oxide layer is deposited on a lower metal interconnection layer
40
to form a lower insulating interlayer
42
, on which is deposited a nitride layer to an etching stopper layer
44
, on which is deposited an oxide layer to form an upper insulating interlayer
46
. The substrate is subjected to a photolithographic process to sequentially etch the upper insulating interlayer
46
, etching stopper layer
44
, and lower insulating interlayer
42
so as to form the contact hole
48
, exposing the lower metal interconnection layer
40
. Deposited over it is a photoresist pattern
50
to etch the upper insulating interlayer
46
with high selectivity to the etching stopper layer
44
to form the trench
52
. This process also increases the parasitic capacitance among the metal interconnections due to the nitride stopper layer having high dielectric constant.
FIG. 4
illustrates another conventional CBDD process in which an oxide layer is deposited on a lower metal interconnection layer
60
to form an insulating interlayer
62
, which is subjected photolithographic process to etch the contact hole
64
exposing the lower metal interconnection layer. Deposited on it is a photoresist, etched back. The contact hole
64
is filled with the photoresist
66
. Formed over the insulating interlayer
62
is a photoresist pattern
68
to etch the insulating interlayer
62
to form the trench
70
with a predetermined depth. Finally, the photoresist pattern
68
and the photoresist
66
filling the contact hole
64
are removed. Although this process does not increase the parasitic capacitance of the metal interconnections because of etching the trench by using the photoresist instead of a nitride layer, this process requires an additional step of filling the trench with photoresist, and does not secure uniformity of the trench depth because of the lack of an etching stopper layer like a nitride layer used in the insulating interlayer.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of forming metal interconnections in a semiconductor device by selectively etching trenches with the help of low dielectric constant insulating layers for the damascene process.
According to an aspect of the present invention, a method of forming metal interconnections in a semiconductor device comprises the steps of depositing a first, lower insulating layer having a low dielectric constant over a semiconductor substrate provided with a metal interconnection layer; depositing over the first insulating interlayer a second, upper insulating layer having a low dielectric constant and a higher etching rate than the first insulating layer; etching the upper and lower insulating interlayers according to a first photoresist pattern formed on the upper insulating interlayer so as to produce contact holes exposing t

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