Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-19
2004-08-17
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S725000, C438S758000
Reexamination Certificate
active
06777321
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a method of forming a buried wiring and an apparatus for processing a substratum.
Studies are being vigorously made for decreasing a dielectric constant of an insulating interlayer used in a semiconductor device.
As one of the methods for decreasing the dielectric constant, studies are being made on the application of a porous insulating layer to an insulating interlayer. Having a low relative dielectric constant (∈), a porous insulating layer is expected to be promising as a raw material for decreasing a capacitance between wiring lines. In principle, a porous insulating layer is conventionally formed by a process of forming a porous structure having solid linkages on the basis of a solidification reaction according to dehydration/condensation in an aqueous solution containing tetraethoxysilane (TEOS) and ammonia (NH
3
), and then drying off the aqueous solution.
And, a metal wiring is formed by a so-called damascene process in which a lithography method and a dry etching method are used to form a groove (trench) portion and/or a hole portion in the porous insulating layer formed according to the above process, a barrier metal and a metal material such as aluminum and copper are filled in the groove portion and/or the hole portion and deposited on the porous insulating layer, and further, the metal material and the barrier metal deposited on the porous insulating layer are removed by a chemical/mechanical polishing method (CMP method).
Further, a hollow wiring method is available as one of the methods of decreasing the capacitance between wiring lines. In the hollow wiring method, an insulating interlayer between wiring lines is removed to bring the space between the wiring lines into a hollow state, and air which substantially has a relative dielectric constant of 1 is used as an insulating substance. This method is disclosed, for example, in “Semiconductor International”, July 1999, page 125. This hollow wiring method is already put to practical use for broad aluminum wiring lines in which a wiring line width is several microns or more.
For overcoming problems in the hollow wiring method, there is proposed a method in which a hollow portion between wiring lines is filled with a solid insulating layer. In this method, metal wiring lines are formed in an insulating layer composed of a phosphorus silicate glass (PSG), and then, the insulating layer is removed by a drying etching method in which the insulating layer is exposed to a gas containing hydrogen fluoride (HF) or plasma thereof. At this stage, the space between the wiring lines is brought into a hollow state, and the space between the wiring lines is filled with a gas. Then, a porous insulating layer having a low relative dielectric constant is grown from the surface of the metal wiring line by a chemical vapor deposition method (CVD method) to fill the porous insulating layer in the space between the wiring lines.
In the method using an insulating interlayer composed of a porous insulating layer, however, it is difficult to form a groove portion and/or a hole portion having a desired form in the porous insulating layer under good control by a dry etching method. There is another problem that the porous insulating layer is damaged when a photoresist used in a lithography method is removed, so that the porous insulating layer is altered in chemical properties and form. For avoiding this problem, it is required to keep the porous insulating layer not being exposed to an atmosphere employed for the photoresist removal. For this purpose, an addition step is required. There is still another problem that, when a metal material and a barrier metal deposited on the porous insulating layer is removed by a CMP method, the porous insulating layer having low mechanical strength is broken due to a shear force exerted on the porous insulating layer. For preventing this problem, it is required, on a CMP process, to set a polishing rate at a level at which the shear force on the porous insulating layer is lower than a shear force which breaks the porous insulating layer. However, this procedure involves a problem that the polishing rate of the metal material and the barrier metal deposited on the porous insulating layer is decreased, which results in a longer throughput.
Further, the hollow wiring method has the following problem when it is applied to an LSI wiring having a wiring line width of 1 &mgr;m or less. That is, a solution containing hydrofluoric acid is often used for removing a silicon-containing insulating interlayer, and a stress is caused between wiring lines due to a surface tension of water droplets formed between the wiring lines just before drying is finished in a drying step after a washing step. As a result, the wiring line may be mechanically deformed due to the above stress, which results in destruction. Further, if the drying is made possible by taking measures against the surface tension, the following problem takes place. That is, as the circuit operates, voltages of the wiring lines undergo changing. In this case, a local condenser having a potential difference between the adjacent wiring lines repeats charging and discharging, and due to the accumulation of a charge and the discharging, a Coulomb force between the adjacent wiring lines changes. As a result, the wiring lines vibrate, and when the vibration takes place intensely, the wiring lines may break due to the mechanical wearing of the wiring lines or a short circuit may be generated between the adjacent wiring lines. These problems make it difficult to apply the hollow wiring method to fine wiring lines in which a distance between the wiring lines is small.
In the method in which a hollow portion between wiring lines is filled with a solid insulating layer, a source gas used in the CVD method is fed from the top surface of each wiring line to side surfaces of each wiring line, so that an insulating layer is formed on the top surface earlier than it is formed on the side surfaces. Therefore, the insulating layer is formed on the top portions of the adjacent wiring lines before the insulating layer is formed in the bottom portions of the wiring lines and before a space between the lower portions of the adjacent wiring lines is filled with the insulating layer, so that a space between the upper portions of the adjacent wiring lines is filled with the insulating layer. As a result, there is caused a problem that there is a region which is not filled with the insulating layer between the wiring lines. Due to this problem, it is difficult to realize the technology of filling a hollow portion by removing the insulating layer in a gaseous phase and forming a new insulating layer in a gaseous phase. Further, there is another problem that a device isolation region and a gate insulating layer of a transistor portion are damaged with an etching gas used for removing the insulating layer by a dry etching method.
OBJECT AND SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of forming a buried wiring, in which high reliability is accomplished, the wiring is neither damaged nor broken, an insulating layer used for burying the wiring is not damaged, and an insulating material can be reliably filled between the wirings.
It is another object of the present invention to provide an apparatus for processing a substratum which apparatus is suitable for practicing the above method of forming a buried wiring.
According to the present invention, the above object of the present invention is achieved by a method of forming a buried wiring, which method comprises the steps of:
(A) forming a wiring and a first insulating layer filled between the wirings on a substratum,
(B) immersing the first insulating layer in a fluid which can dissolve the first insulating layer, to dissolve the first insulating layer into the fluid,
(C) substituting, for the fluid, a raw material solution containing a raw material for forming a second insulating layer, with
Fukumoto Yoshito
Ikeda Koichi
Kawakami Nobuyuki
Kinoshita Takashi
Komai Naoki
Chen Jack
Huynh Yennhu B.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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