Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-13
2002-05-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S589000, C438S620000, C438S977000, C438S967000, C438S705000, C438S795000
Reexamination Certificate
active
06383924
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods of making such devices. More particularly, the invention relates to solid state materials and to a novel method of forming buried conductor patterns in such solid state materials.
BACKGROUND OF THE INVENTION
Monocrystalline solid state materials such as single-crystal semiconductors are the basis of the current microelectronics industry. Solid state materials are characterized by a variety of properties, for example, electrical properties such as electrical conductivity or charge mobility, optical properties such as refractive index or speed of photons, thermal properties such as thermal conductivity or thermal expansion, mechanical properties such as stress or strain curves, and chemical properties such as resistance to corrosion or reaction consistency, among others.
Over the past years, the semiconductor industry has constantly explored new ways of increasing the amount of active surface area on the integrated circuit chips, particularly on those employing monocrystalline semiconductor substrates. Accordingly, attempts to modify the electrical, optical, thermal and/or mechanical properties of such monocrystalline substrates have been made in an effort to minimize the dimensions of the IC devices, while maximizing the corresponding available active area. For example, new epitaxial growth processes such as the Epitaxial Lateral Overgrowth (ELO) have been used in an attempt to extend the amount of surface area available to active devices. However, these growth processes had limited results mainly because they consume part of the precious surface areas for seeding purposes, defeating therefore the primary purpose of increasing the available active area.
Another technology proposed by the semiconductor industry is the so-called Silicon-On-Insulator (SOI) process, wherein oxygen atoms are implanted at high dose and energy to form a silicon dioxide insulating layer between the upper surface of the original monocrystalline substrate and the bottom bulk portion of the same substrate. Although the SOI devices have many advantages, such as reduced parasitic capacitance due to the buried insulating layer, the process is relatively expensive because of the high costs of implanting the oxygen atoms and curing of the implant-induced defects.
Accordingly, there is a need for an improved method of increasing the available active surface area on integrated circuit chips fabricated on monocrystalline substrates. There is also a need for a more advantageous method of forming monocrystalline superconducting substrates for low power and high speed microelectronics devices, as well as a method for minimizing the cost of fabricating such substrates. There is further a need for an improved metallization scheme which facilitates the formation of active devices on SOI substrates and on the more novel Silicon-On-Nothing (SON) substrates.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a plurality of buried conductors and/or buried plate patterns in semiconductor substrates, such as monocrystalline silicon substrates. According to an exemplary embodiment of the invention, a plurality of empty-spaced buried patterns are formed in a monocrystalline substrate. Holes are next formed in the monocrystalline substrate to connect surfaces of the substrate with the previously formed empty-spaced patterns. The whole assembly is subsequently exposed to an oxidizing atmosphere so that the inner surfaces of the empty-spaced patterns are oxidized. The empty-spaced patterns are then filled with a suitable conducting material by suitable methods.
These and other features and advantages of the invention will be more clearly apparent from the following detailed description which is provided in connection with accompanying drawings and which illustrates exemplary embodiments of the invention.
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Sato et al., “A New Substrate Engineering for the Formation of Empty-Space in Silicon (ESS) Induced by Silicon Surface Migration,” 1999 IEEE, pp 517-520.*
F.A. Nichols, et al.—“Surface- (Interface-) and Volume-Diffusion Contributions to Morphological Changes Driven by Capillarity,” Transactions of the Metallurgical Society of AIME, vol. 233, Oct. 1965, pp. 1840-1848.
Tsutomu Sato, et al.—“A New Substrate Engineering for the Formation of Empty Space in Silicon (ESS) Induced by Silicon Surface Migration,” 1999 IEEE, pp. 517-520.
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Farrar Paul A.
Geusic Joseph
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Niebling John F.
Zarneke David A.
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