Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-22
2003-12-02
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000
Reexamination Certificate
active
06656828
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a technique effective for application to a chip size package (CSP) in which bump electrodes disposed in an area on a chip and bonding pads are electrically connected to each other through Cu interconnections.
BACKGROUND ART
In a process of manufacturing a high-speed LSI which operates at a high frequency, it is indispensable to adopt a low-resistant interconnection material and an insulating film material having a low dielectric constant to reduce electric resistance in an interconnection and capacity between interconnections. Since Cu has low electric resistance which is about two third of that of Al and has high EM (electromigration) resistance, Cu is being used more and more for a high speed logic LSI, a microcomputer, and the like which need a low-resistant fine interconnection.
A Cu interconnection is formed by what is called the Damascene process of burying a Cu film in a groove or a through hole formed in an insulating film for the reason such that a photoresist having excellent etch selectivity has not been developed yet. When the Cu film is buried, plating, sputtering, or the like is used. Since it is requested to bury a Cu film in a groove or a through hole having a high aspect ratio to form a fine interconnection, plating having excellent burying characteristics is more advantageous than sputtering.
Cu has, however, the following problems. (a) Cu has oxidation resistance lower than that of Al. Oxidation progresses to the inside of an interconnection by heat or the like generated at the time of depositing an insulating interlayer, and electric resistance increases. (b) Cu has low strength of bonding to an insulating material including oxygen such as silicon oxide or polyimide resin. (c) Cu is easily diffused into silicon and a silicon oxide. When Cu is in contact with a diffusion layer of the substrate, the characteristics of a device deteriorate. In the process of manufacturing an LSI using Cu as a material of an interconnection, countermeasures against those problems are necessary.
Japanese Unexamined Patent Application No. Hei 4(1992)-309229 discloses a technique of covering the surfaces (top and under faces and both sides) of a Cu-based interconnection with a thin oxidation preventing layer to prevent oxidation of the Cu-based interconnection, to prevent diffusion of Cu into silicon and a silicon oxide, and to improve adhesion to a silicon oxide film. The oxidation preventing layer is made of an oxide or nitride stabler than a Cu oxide, such as a refractory metal silicide containing free silicon, an alloy of Cu and another metal or silicon, or refractory metal nitride.
Japanese Unexamined Patent Application No. Hei 5(1993)-102318 discloses a technique such that, when a plug made of a Cu alloy is formed in a connection hole (via) opened in an insulating layer containing oxygen, a thin layer made of an oxide of the alloy element (for example, chromium oxide or aluminum oxide) on a top face of the Cu alloy plug and a contact face with the insulating layer containing oxygen. The thin film layer functions as an adhesion layer, diffusion barrier for preventing the diffusion of Cu, and also as a surface protective layer to provide the Cu alloy with corrosion resistance.
Japanese Unexamined Patent Application No. Hei 9(1997)-36115 discloses a technique of forming a Cu interconnection in a groove by forming a plurality of grooves at predetermined intervals in an insulating interlayer, depositing a Cu thin film on the insulating interlayer so as to bury the grooves, and removing the Cu thin film on the insulating interlayer by chemical mechanical polishing (CMP) or the like. To reduce parasitic capacity between Cu interconnections, the insulating interlayer in which grooves are formed is made of a photosensitive polyimide resin having a lower dielectric constant than that of silicon oxide or silicon nitride. A thin Cr layer as a metal underlayer of the Cu interconnection is formed on the bottom and side walls of the groove. By the Cr layer, close adhesion between the Cu interconnection and the photosensitive polyimide resin is assured, and the oxidation of the contact face with the silicon oxide film as an underlayer, of the Cu interconnection is prevented.
The inventors of the present invention are now developing a process for manufacturing a high speed LSI by a fine design rule of 0.2 &mgr;m or smaller. To improve the operating speed of the chip, the high speed LSI employs the flip chip bonding by which the distance between a connection terminal on the outside of a chip to a mother board can be made shortest. The high speed LSI also adopts an area array structure in which bump electrodes serving as external connection terminals are arranged in a central area on a chip.
The area array structure has an advantage such that a number of pins can be arranged more easily as compared with a structure (peripheral structure) in which bump electrodes are arranged on bonding pads arranged in the peripheral area of the chip. In the area array structure in which a wider space can be assured between neighboring bump electrodes, a larger diameter of the bump electrode can be allowed. Consequently, stress which occurs due to a difference between a coefficient of thermal expansion of the chip and that of the mother board can be lessened by the bump electrodes, so that the reliability of connection of the chip is increased.
To manufacture an LSI having the area array structure, interconnections for connecting bonding pads arranged in the peripheral portion of the chip and bump electrodes arranged in the whole surface of the chip, what is called re-arrangement interconnections are necessary. In the case of an LSI in which emphasis is placed on high-speed operation, it is desirable to make the re-arrangement interconnections of Cu for the above-described reasons.
It is also desirable to form the re-arrangement interconnections in a wafer process (pre-process) more than in an assembling process (post-process) which is performed after a wafer is diced into chips. Specifically, formation of the re-arrangement interconnections and the following formation of bump electrodes is performed in the wafer process, after that, a wafer is divided into a plurality of chips, and chip size packages (CSP) are formed. In such a manner, the package assembling process (post-process) becomes unnecessary. Thus, a CSP adapted to a high packing density and high-speed operation can be manufactured at low cost and in a short period of development.
The inventors examined processes as follows to manufacture a CSP in which bump electrodes arranged in an area on the chip and bump electrodes are electrically connected via the re-interconnections of Cu.
First, in a manner similar to a normal wafer process, semiconductor elements are formed on the principal face of a wafer, a plurality of interconnections (signal interconnections and power source interconnections) are formed on the semiconductor elements, and a passivation film is formed on the uppermost interconnection. The passivation film is a closely-packed insulating film such as a silicon nitride film (or a stacked film of a silicon nitride film and a silicon oxide film) formed by plasma CVD, and functions as a surface protective film for preventing intrusion by moisture and a foreign matter into an integrated circuit from the wafer surface.
Subsequently, a polyimide resin layer is formed on the passivation film, the polyimide resin layer and the passivation film under the polyimide resin layer are etched to expose a part of the uppermost interconnection, thereby forming a bonding pad. The bonding pads are arranged along the peripheral portion of the chip area defined on the principal face of the wafer.
A Cu film is deposited by sputtering on the polyimide resin layer and the bonding pads to thereby form a feeder layer. A photoresist film formed on the feeder layer is exposed and developed, thereby forming a long
Maitani Touta
Nishihara Shinji
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Thomas Tom
Vu Hung Kim
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