Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-12-19
2003-09-16
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S286000
Reexamination Certificate
active
06620656
ABSTRACT:
FIELD OF THE INVENTION
The invention related generally to semiconductor devices and more particularly to a body-tied silicon-on-insulator semiconductor device structure and method therefore.
RELATED ART
Silicon on insulator (SOI) technology has been developed to provide a number of advantages over bulk silicon device technologies. As is known, SOI provides improvements in speed and power consumption with respect to previous bulk silicon circuits. Some of the benefits of SOI technology are based on the reduced capacitance at various junctions within semiconductor devices, whereas additional benefits are derived from the floating body itself.
Because the speed with which a floating body device switches may be affected by the previous state of the device, undesirable variations in switching speed may occur. Therefore, although floating body coupling can provide advantages for some portion of the circuit built using SOI technology, in some cases a known body potential for specific devices is desired. As such, knowledge of the potential of the body in a body-tied SOI device ensures that the switching characteristics of the device are reproducible and predictable regardless of the previous state of the device.
In order to allow for body-tied devices within SOI circuits, some device structures have been developed that provide a means for tying the active area of individual devices to a known potential. Examples include T-and H-gate transistor structures where the active area extends beyond the gate structure to provide a means for supplying the desired potential to the active area. The T-and H-gate structures have a significant amount of added gate capacitance and are also problematic in terms of process control issues. As a result of the additional gate capacitance, significant reduction of device speed can occur when T-and H-gate structures are used.
In other prior art techniques for controlling the potential within active areas in SOI devices, a uniform biasing potential may be applied to all of the devices in a well by linking the bodies of these devices underneath the field oxide. Although this does ensure that the potential within the bodies of the transistors is known, it does not allow devices that have known body potential to coexist with floating body devices. Thus, as floating body devices are desirable for some portions of the circuit and whereas body-tied devices are desirable for other portions of the circuit, such techniques are hindered by undesirable limitations. Furthermore, by linking the bodies of the transistors within the well structure, some of the isolation advantages provided by SOI technology are forfeited. For example, some of the advantages in terms of avoiding latch-up and leakage are diminished.
Therefore, a need exists for a body-tied SOI device that does not suffer from the adverse effects associated with increased gate capacitance and reduced isolation integrity while providing adequate assurance as to active area potential such that the switching characteristics of the device are well understood.
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PCT International Search Report.
Kang Laegu
Mendicino Michael A.
Min Byoung W.
Clingan, Jr. James L.
Motorola Inc.
Tsai Jey
Vo Kim-Marie
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