Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Patent
1998-06-23
2000-12-05
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
438467, 438600, H01L 2182
Patent
active
061565881
ABSTRACT:
The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.
REFERENCES:
patent: 4914055 (1990-04-01), Gordon et al.
patent: 5120679 (1992-06-01), Boardman et al.
patent: 5328865 (1994-07-01), Boardman et al.
Delgado Miguel A.
Sanchez Ivan
Jr. Carl Whitehead
VLSI Technology Inc.
Vockrodt Jeff
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