Method of forming an ohmic contact to a III-V semiconductor mate

Details Method of forming an ohmic contact to a III-V semiconductor mate Method of forming an ohmic contact to a III-V semiconductor mate

1994-07-01

2000-05-02

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438604, 438571, 438576, 438606, H01L 2144

Patent

active

060572191

ABSTRACT:
An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.

REFERENCES:
patent: 4745082 (1988-05-01), Kwok
patent: 5010039 (1991-04-01), Ku et al.
patent: 5144410 (1992-09-01), Johnson
R Piato et al. "Reactive Ion Etching in SF.sub.6 Gas Mixtures" J. Electro. Soc. Jan. 1987, vol. 134 #1, pp. 165-175.
H. Oigawa et al., "Stabilization of GaAs Surface/Interface by Sulfur Treatment", SSDM, 1988, pp. 263-266.
E. Yablonovitch et al., "Nearly Ideal Electronic Properties of Sulfide Coated GaAs Surfaces", Applied Physics Letter 51(6), Aug. 1987, pp. 439-441.
M.S. Carpenter et al., "Schottky Barrier Formation on (NH.sub.4).sub.2 S-Treated n- and p-type (100)GaAs", Applied Physics Letter 53(1), Jul. 1988, pp. 66-68.
D. Liu et al., "Deep Level Transient Spectroscopy Study of GaAs Surface States Treated with Inorganic Sulfides", Applied Physics Letter 53(12), Sep. 1988, pp. 1059-1061.
B.A. Cowans et al., "X-ray Photoelectron Spectroscopy of Ammonium Sulfide Treated GaAs (100) Surfaces", Applied Physics Letter 54(4), Jan. 1989, pp. 365-367.
D. J. Spindt et al., "Photoemission Study of the Band Bending and Chemistry of Sodium Sulfide on GaAs (100)", Applied Physics Letter 54(12), Mar. 1989, pp. 1148-1150.
M.S. Carpenter et al., "Investigations of Ammonium Sulfide Surface Treatments on GaAs", J. Vac. Sci. Technol. B7(4), Jul./Aug. 1989, pp. 845-850.
W.E. Spicer et al., "Pinning and Fermi Level Movement at GaAs Surfaces and Interfaces", J. Vac. Sci. Technol. A8(3), May/Jun. 1990, pp. 2084-2089.
J. Shin et al., "Sulfur Bonding to GaAs", J. Vac. Sci. Technol. B9(4), Jul./Aug. 1991, pp. 2337-2341.
H. Sugahara et al., "Synchrotron Radiation Photoemission Analysis for (NH.sub.4).sub.2 S.sub.x -treated GaAs", J. Appl. Phys. 69(8), Apr. 1991, pp. 4349-4353.
H. Kawanishi et al., "Adsorption and Desorption of Sulfur on a GaAs (001) Surface by H.sub.2 S Exposure and Heat treatment", J. Vac. Sci. Technol. B9(3), May/Jun. 1991, pp. 1535-1539.
H. Kawanishi et al., "Reaction of Oxygen with in Situ H.sub.2 S-treated GaAs (001) Surfaces", J. Appl. Phys. 70(2), Jul. 1991, pp. 805-810.
C. Wan et al., "Comparison of Self-Aligned and Non-Self-Aligned GaAs E/D MESFET's", 1989, pp. 839-845.
C.F. Wan et al., A Comparison Study of GaAs E/D-MESFETs Fabricated with Self-Aligned and Non-Self-Aligned Processes, IEEE, 1997, pp. 133-136.
M. Ino et al., "A 1.2 NS GaAs Read-Only-Memory Fabricated by 0.5 mm-Gate BP-Saint", IEEE. 1987, pp. 189-192.
J. Cho et al., "Doping of GaAs Using SF.sub.6 Plasma Treatment", J. Appl. Phys. 74(12), Dec. 1993, pp. 7315-7320.
K. Wakamoto et al., "A True Off-Site Self-Aligned Process for High Efficiency Ku-Band Power Fets", IEEE, 1989, pp. 1023-1026.
T. Tambo et al., "Low-Noise GaAs MESFET by Dummy-Gate Self Alignment Technology for MMIC", IEEE, 1987, pp. 49-52.
Y.D. Shen et al., An Ultra High Performance Manufacturable GaAs E/D Process, IEEE, 1987, pp. 125-128.
J. Kleks et al., "A 4-Bit Single Chip Analog to Digital Converter with a 1.0 Gigahertz Analog Input Bandwidth", IEEE, 1987, pp. 79-82.
N. Matsunaga et al., "Gallium Arsendide Mesfet Technologies with 0.7 mm Gate-Length for 4kb 1nd Static Ram", IEEE, 1987, p. 129-132.
T. Enoki et al., "0.3-mm Advanced Saint FET's Having Asymmetric n.sup.+ -Layers for Ultra-High Frequency GaAs MMIC's", IEEE, 1988, pp. 18-24.
S. Susa, "Comparisons of GaAs, Tungsten, and Photoresist Etch Rates and GaAs Surfaces Using RIE with CF.sub.4, CF.sub.4 +N.sub.2, and SF.sub.6 +N.sub.2 Mixtures", J Electrochem. Co.: Solid-State Science and Technology, Nov. 1985, vol. 32, No. 11, pp. 2762-2767.
R. Pinto et al., "Reactive Ion Etching in SF6 Gas Mixtures", J. Electrochem Soc.: Solid-State Science and Technology, Jan. 1987, vol. 134, No. 1, pp. 165-175.
P. O'Neil et al., "Motorola Readies Low Cost GaAs Process for Commercialization", No Date.
K. Yamasaki et al., "GaAs LSI-Directed MESFET's with Self-Aligned Implantation for n.sup.+ -Layer Technology (SAINT)", IEEE, 1982, pp. 1772-1777.
R. Vantuyl et al., "A Manufacturing Process for Analog and Digital Gallium Arsenide Integrated Circuits", IEEE, 1982, pp. 1031-1038.
K. Ueno et al., "A High Transconductance GaAs MESFET with Reduced Short Channel Effect Characteristics", IEEE, 1985, pp. 82-85.
K. Yamasaki et al., "Self-Align Implantation for n+-Layer Technology (SAINT) for High-Speed GaAs ICs", Electronics Letters, Feb. 1982, pp. 119-121.

Affiliated with

Also associated with

Rating

Method of forming an ohmic contact to a III-V semiconductor mate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming an ohmic contact to a III-V semiconductor mate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming an ohmic contact to a III-V semiconductor mate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1593463