Method of forming an integrated circuit on a low loss substrate

Details Method of forming an integrated circuit on a low loss substrate Method of forming an integrated circuit on a low loss substrate

2001-07-03

2002-12-03

Nguyen, Viet Q. (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S960000

Reexamination Certificate

active

06489217

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly, to formation of such a circuit on a low loss substrate.
2. Prior Art
Semiconductor devices in the form of integrated circuits are important in telecommunications systems involving a broad spectrum of different circuits. These circuits may have high frequency capabilities. High frequency telecommunications circuits typically involve the use of inductors to either tune a circuit to a particular desired frequency, to perform critical circuit functions such as maintaining a critical current flow, or to filter and eliminate undesired electrical noise from desired signals. Since the use of discrete inductors that are separate from the integrated circuit may give rise to implementation problems, the high frequency circuit design has been moving in the direction of integrating as many of these needed inductors as possible into the semiconductor device itself.
The quality factor (Q) of an inductive circuit is a figure of merit that relates the energy stored to the energy dissipated or lost. High Q inductor circuits (a Q of 10 or greater) conserve sufficient energy to allow an appropriate inductive response. Alternately, low Q inductor circuits (a Q of 3 or less) lose a sufficient portion of the energy applied causing them to perform poorly as inductive elements.
An example of a typical integrated circuit, used in many current communications microchips, has a highly conductive substrate and a moderately resistive epitaxial (EPI) layer grown on the substrate. However, this design may not be conducive for supporting a high Q inductor. An integrated inductor formed over the EPI layer may induce eddy currents into the highly conductive substrate thereby incurring a large energy loss. To be energy efficient and therefore low loss, the integrated inductor would have to be formed over a highly resistive substrate.
SUMMARY
The present invention, in one aspect, describes a method for manufacturing an integrated circuit structure. The method includes providing a layer of porous silicon, and epitaxially growing a high resistivity layer on the layer of porous silicon. Devices are then formed on the high resistivity layer to produce the integrated circuit structure. The integrated circuit structure is attached to a silica substrate, such that the silica substrate is coupled to the devices. Further, surface contacts are provided on the structure. The layer of porous silicon is then removed.
In another aspect, the present invention describes an integrated structure. The structure includes a layer of porous silicon, a high resistivity layer, a plurality of circuit devices, a silica substrate, and surface contacts. The high resistivity layer is epitaxially grown on the layer of porous silicon. The plurality of circuit devices is formed on the high resistivity layer to produce the integrated circuit structure. The silica substrate is attached to the integrated circuit structure, such that the silica substrate is coupled to the circuit devices. Surface contacts provide connections to the circuit devices.


REFERENCES:
patent: 6143629 (2000-11-01), Sato
patent: 6143929 (2000-11-01), Sato
patent: 6376285 (2002-04-01), Joyner et al.
patent: 6376859 (2002-04-01), Swanson et al.

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