Method of forming an integrated circuit device having cyanate es

Details Method of forming an integrated circuit device having cyanate es Method of forming an integrated circuit device having cyanate es

1999-02-25

2000-05-09

Niebling, John F.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

438108, 438902, 29841, 29855, H01L 2144, H01L 2148, H01L 2150

Patent

active

060603437

ABSTRACT:
An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

REFERENCES:
patent: 3755402 (1973-08-01), Grigat et al.
patent: 3994949 (1976-11-01), Meyer et al.
patent: 4022755 (1977-05-01), Tanigaichi et al.
patent: 4056681 (1977-11-01), Cook, Jr.
patent: 4330658 (1982-05-01), Ikeguchi et al.
patent: 4740584 (1988-04-01), Shimp
patent: 4820855 (1989-04-01), Gaku et al.
patent: 5026667 (1991-06-01), Roberts, Jr.
patent: 5034801 (1991-07-01), Fischer
patent: 5102718 (1992-04-01), Tingerthal et al.
patent: 5132778 (1992-07-01), Juskey et al.
patent: 5137846 (1992-08-01), Machuga et al.
patent: 5194930 (1993-03-01), Papathomas et al.
patent: 5198695 (1993-03-01), Hanes et al.
patent: 5268193 (1993-12-01), Beuhler et al.
patent: 5300735 (1994-04-01), Yokono et al.
patent: 5388328 (1995-02-01), Yokono et al.
patent: 5438022 (1995-08-01), Allman et al.
patent: 5504374 (1996-04-01), Oliver et al.
patent: 5530288 (1996-06-01), Stone
patent: 5563380 (1996-10-01), Restoker et al.
patent: 5569493 (1996-10-01), Granger et al.
patent: 5571740 (1996-11-01), Peterson
patent: 5579573 (1996-12-01), Baker et al.
patent: 5604978 (1997-02-01), Sherif et al.
patent: 5605781 (1997-02-01), Gelorme et al.
patent: 5656862 (1997-08-01), Papathomas et al.
patent: 5660920 (1997-08-01), Buckley et al.
patent: 5667884 (1997-09-01), Bolger
Shimp et al., Arocy.COPYRGT. Cyanate Ester Resins Chemistry, Properties and Applications, Second Edition, 1-36 (1990).

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