Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-12-28
2004-02-17
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S184000, C438S626000, C438S637000, C438S640000
Reexamination Certificate
active
06693029
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and methods for manufacturing substrates thereof, and more particularly to a semiconductor device and a method for manufacturing a substrate of the semiconductor device, in which one or a plurality of semiconductor chips are mounted on the substrate thereof.
In recent years, with increasing development of semiconductor chips with high density, the number of terminals provided on the semiconductor chips has also increased. Currently, a semiconductor devices such as a BGA (ball grid array) type semiconductor device or the like, where a semiconductor chip(s) is (are) mounted on a substrate thereof, has been widely used all over the world.
Accordingly, the substrate where the semiconductor chip(s) is (are) mounted is also required to have density high enough to support the increase in the number of the terminals of the mounted semiconductor chip(s).
2. Description of the Related Art
Conventionally, the substrate of the semiconductor device commonly has a multi-layer structure. In the well-known multi-layer structure, a build-up layer is applied to a ceramic multi-layer substrate or to a print wiring substrate by means of a build-up process. The semiconductor chip(s) may be bonded to the multi-layer substrate in a face-down state.
With respect to a method of manufacturing the multi-layer substrate, in a case of the ceramic multi-layer substrate, the method may comprise the steps of:
forming a plurality of via-holes in a green sheet;
filling the plurality of via-holes with conductive materials such as tungsten pastes and so on;
forming a wiring pattern on the green sheet by means of a printing process;
stacking a plurality of the green sheets and then pressing them together; and
sintering the pressed green sheets by a sintering process.
In a case of the printed multi-layer substrate, the method may comprise the steps of:
forming a pattern on a glass-epoxy layer with copper leaf;
stacking a plurality of the glass-epoxy layers with adhesive;
forming a plurality of through-holes on the glass-epoxy layers with a drill;
plating the through-holes with copper so as to form a core substrate available for making electrical interconnections among the layers;
forming an insulation layer on the core substrate; and
forming a wiring pattern on the insulation layer by means of a subtractive process or a semi-additive process, and then repeating this step until the build-up layer is completed.
Further, Japan Laid-open Patent Application No. 11-54934 discloses a multi-layer wiring substrate for the semiconductor device. The disclosed multi-layer wiring substrate is formed such that a plurality of filmy single-side circuit substrates are stacked on both two opposing surfaces of the core substrate where a plurality of the through-holes are formed.
The filmy single-side circuit substrates each includes an insulation base and an adhesive layer that is provided on the insulation base. The insulation base has a plurality of via-holes and a wiring layer connected to the plurality of via-holes. Further, on the plurality of via-holes, there are respectively provided a plurality of bumps that protrude from the insulation base and are electrically connected to the via-holes.
Since the adhesive layer is provided on the insulation base, the plurality of bumps is positioned within the adhesive layer. The single-side circuit substrates, which are thus configured, are stacked together by means of a pressing-and-heating process, and the inter-layer connection is realized by connecting the plurality of bumps to the wiring layer.
However, in a case where the ceramic multi-layer substrate is used as a semiconductor device substrate, since the wiring pattern is formed by means of the printing process, this case suffers from a disadvantage that there is a limit to form a fine pattern. For this reason, the ceramic multi-layer substrate are not suitable for the semiconductor device where the density of the semiconductor chip(s) mounted thereon is further increased as well as the number of the connecting terminals.
Further, it should be considered that the green sheet shrinks during sintering of the ceramic multi-layer substrate. For this reason, land diameters thereof must be designed big enough to receive the inter-layer vias. But this also suffers from a disadvantage that wiring rules cannot be made fine enough. Furthermore, another disadvantage of widely using the ceramic multi-layer substrate is the high cost of ceramic materials.
On the other hand, in a case where the print substrate is used as the semiconductor device substrate on which the build-up layer is formed and the fine wires are laid, the semiconductor device substrate can become a multi-layer substrate by repeating a process of laying the wires and forming the vias on each layer by means of a film forming technology such as the exposing and the developing. However, this case is costly, time-consuming, and limited in the number of the stacked layers.
Moreover, Japanese Laid-open Patent Application No. 11-54934 discloses a multi-layer wiring substrate. In the disclosed multi-layer wiring substrate, a single-side circuit substrate includes an insulation substrate and an adhesive layer, where the via-holes are formed on the insulation substrate and bumps are formed on the adhesive layer. In this configuration, however, the via-holes and the bumps should be joined to each other on a boundary surface between the insulation substrate and the adhesive layer.
Thus, the via-holes and the bumps are provided separately and thereby the strengths on joints between the via-holes and the bumps become weak. Accordingly, during the mounting of the semiconductor device, the insulation substrate and the adhesive layer are heated, and a stress resulting from a difference in coefficient of thermal expansion therebetween is applied to the joints between the via-holes and the bumps. As a result, the joints between the via-holes and the bumps may be damaged by the stress.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor device and a method for manufacturing a substrate thereof, in which the above disadvantages can be overcome.
Another and a more specific object of the present invention is to provide a semiconductor device and a method for manufacturing the substrate thereof, in which high density, high reliability and low cost of wire layers and vias provided therein can be achieved.
The above objects and other objects of the present invention are achieved by a semiconductor device, comprising:
a substrate having a plurality of organic insulation substrate layers and a plurality of adhesive layers which are alternatively stacked, and inter-layer wires which are laid among said stacked layers and are electrically interconnected by using vias; and
a semiconductor chip mounted on said substrate;
said vias each having a via-hole which is formed penetrating said organic insulation substrate layers and said adhesive layers and a metal via member which is disposed in said via-hole and made of an identical material.
The above-mentioned objects of the present invention can be obtained by a method for manufacturing a substrate, said substrate having a plurality of organic insulation substrate layers and a plurality of adhesive layers which are alternatively stacked, and inter-layer wires which are laid among said stacked layers and are electrically interconnected by using vias formed by providing metal materials in via-holes,
said manufacturing method comprising the steps of:
(a) stacking said adhesive layers and said organic insulation substrate layers alternatively so as to form a substrate body;
(b) forming said via-holes such that said via-holes penetrate said substrate body;
(c) forming a conductive metal film so that the conductive metal film covers said via-holes on one side of said substrate body;
(d) using an electrolytic plating process, where said conductive metal film is used as an electrode, to form said metal
Iijima Makoto
Morioka Muneharu
Nukiwa Masaru
Ueno Seiji
Fujitsu Limited
Luhrs Michael K.
Westerman Hattori Daniels & Adrian LLP
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