Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-11-26
2003-05-20
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S781000
Reexamination Certificate
active
06566229
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a device isolation layer in a semiconductor device and, more particularly, to a method of forming a trench-type device isolation layer using an SOG (spin on glass) layer.
2. Description of Related Art
As the integration level of semiconductor devices increases, shallow trench isolation (STI) type device isolation layers are increasingly being used. In a device isolation method employing STI, an oxide layer fills a trench that is formed by etching a semiconductor substrate. The STI technique is used to avoid a “bird's beak” phenomenon resulting from a conventional technique such as local oxidation of silicon (LOCOS).
However, an aspect ratio rises rapidly with the trend toward large scale integration circuits (LSI). In other words, a width of a trench to be filled with a device isolation layer decreases while a depth thereof is maintained at the same level. This arrangement makes it necessary to fill up a trench with a void-free or seam-free silicon oxide layer.
Therefore, various approaches have been made for achieving an oxide layer that is capable of filling up a trench having a high aspect ratio. One of the approaches is to form an oxide layer having excellent gap-fill characteristics using TEOS (tetra-ethyl-ortho-silicate), USG (undoped silicate glass) or HDP (high density plasma). However, if an aspect ratio is 5 or higher, a trench is not fully filled with such an oxide layer. As an alternative, use of a layer of SOG (spin on glass) was proposed. Since the SOG is originally liquid or sol-phase, it has excellent gap-fill characteristics to reduce a step difference. Generally, the SOG is coated on a semiconductor substrate.
As an example, hydro silsesquioxane (HSQ) is an example of a SOG, and generally a liquid-phase HSQ layer is coated on a substrate. The coated HSQ layer is first heated using a low temperature (100° C. to 300° C. ), i.e., soft-baked, to remove any solvent ingredients such as dialkyl ether. The HSQ layer coating is then heated at a high temperature (400° C. ), i.e., hard-baked, for over 10 minutes to harden the HSQ layer coating.
Even if the HSQ layer is subject to a hard-bake process in an oxygen ambient, it is scarcely cured. In this case, “cured” means that an element, except oxygen and silicon, is replaced with oxygen to form silicon oxide. When the SOG layer is used to fill a narrow-and-deep void between patterns, it is hard to diffuse oxygen and an oxygen-combined ingredient. Curing occurs at the top surface of the SOG layer, and consequently, the cured top surface portion of the SOG layer prevents oxygen from diffusing into the HSQ layer. Consequently, crystallization of the HSQ layer into a silicon oxide layer occurs slowly. If the HSQ layer is poorly cured, hydrogen remains in the HSQ SOG layer and causes the formation of a porous layer. When this porous layer is subject to a wet etch, the amount of porous layer that is etched over time increases rapidly leading to instability, unreliability and unpredictability in the etching or cleaning process.
A volume shrinkage may also occur while processing the coated HSQ layer, and this may cause the formation of cracks and fissures in a subsequent annealing process. Compared with a well-cured portion, a stress difference occurs during thermal expansion. This leads to the creation of cracks and therefore a lowering of the reliability of the device. As a result, the HSQ layer is not desirable as a composition layer.
In an effort to overcome the foregoing disadvantages, it has been proposed to form a layer of LPCVD TEOS in a trench that is partially filled with HSQ, see “Shallow Trench Isolation Fill for 1 Gbit DRAM and Beyond Using a Hydrogen Silsesquioxane Glass/LPCVD TEOS Hybrid Approach,” contributed to the DUMIC Conference by IBM, 1998. Unfortunately, such an approach requires a separate processing because the conformality of the coating is reduced. If filling a trench with HSQ is beyond a reasonable degree, defects are possibly formed in subsequent process steps.
A method of filling a lower portion of a trench with SOG is disclosed in Japanese Patent Publication No. 2000-183150. First, an organic ingredient is used as SOG to fill a trench for device isolation. In this case, the effects of an oxygen plasma process are not sufficiently transferred to a lower portion of the SOG. This occurs because a plasma-treated upper portion of the SOG is easily etched while a lower portion of the SOG is not or at least insignificantly etched. Thus, the SOG remains at the lower portion of the trench. A remaining portion of the trench is filled with an oxide such as HDP CVD. Such a process is used to fill a trench of a high aspect ratio with an oxide without creating voids or seams. Unfortunately, remaining organic ingredients, such as carbon, have an adverse effect on the insulation of a device isolation layer.
In this regard, the present invention provides a method of forming a trench-type device isolation layer in a trench of a high aspect ratio without the drawbacks and disadvantages of the prior art as described. The present invention also provides a method of forming a trench-type device isolation layer, which can increase a processing margin and enhance characteristics and reliability of products, using spin on glass (SOG) technology.
SUMMARY OF THE INVENTION
According to a preferred embodiment of the present invention, polysilazane is coated on a substrate, in which a trench for device isolation is formed, using a spin on glass (SOG) technique. Using the SOG coating step, the thickness of the coating may be controlled so as to fill only a predetermined portion of the trench with SOG. However, it is preferable that the trench is almost entirely filled with SOG, and then the SOG is etched to a predetermined depth thereby exposing a top portion of the trench. This results in an enhancement of the conformality of the SOG coating.
Preferably, a thin solution containing between about 5 to about 20% polysilizane (a solid-state material decreases in content) is used to maintain a conformal coating thickness without overfilling the trench. More preferably, a polysilazane solution containing between about 5 to about 15 percent by weight, perhydro-polysilazane ([SiH
2
NH]n), which may be easily annealed at a high temperature, is used.
After formation of the SOG layer, a subsequent process is carried out to turn the SOG layer into a silicon oxide layer of silicon dioxide structure. This subsequent process is divided into two steps, baking and annealing. In the baking step, a solvent in the solution is removed. In the annealing step, an organic ingredient or nitrogen and hydrogen ingredients of the polysilazane are replaced with oxygen to initiate the formation of a silicon oxide layer. Preferably, the annealing step is performed prior to a recess step in which the SOG layer is etched to expose a top portion of the trench. Alternatively, the annealing step may be performed subsequent to the recess step. Preferably, the SOG layer is etched down a thickness of 1000 Å from a top surface of the silicon substrate.
Using a CVD technique, a silicon oxide layer is stacked on a remaining SOG layer in which a trench is partially filled. The CVD oxide layer is preferably made of ozone TEOS USG or HDP CVD having good gap-fill properties. After formation of the silicon oxide layer, a planarization step is further carried out using a CMP technique so as to complete a device isolation layer.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
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Goo Ju-Seon
Heo Jin-Hwa
Hong Eun-Kee
Hong Soo-Jin
Kim Hong-Gun
Duy Mai Anh
Fahmy Wael
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
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