Method of forming an encapsulated conductive pillar

Details Method of forming an encapsulated conductive pillar Method of forming an encapsulated conductive pillar

2000-08-25

2003-03-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S626000, C438S627000, C438S629000

Reexamination Certificate

active

06537912

ABSTRACT:

The invention generally relates to microelectronic structures, and more particularly, to an encapsulated three dimensional (3-D) conductive pillar suitable for use with high-dielectric constant materials and a method of formation thereof.
BACKGROUND OF THE INVENTION
Recent efforts for increasing capacitor density on an electronic substrate have focused on using high dielectric constant (HDC) materials as the capacitor dielectric. Currently the most promising dielectrics are perovskites, a family of HDC materials recognized for their excellent charge storage properties. However, with some of these HDC materials (e.g. Ta
2
O
5
, TiO
2
and (Ba,Sr)TiO3 (BST), a good barrier layer with effective diffusion and reaction barrier properties are required since traditional microelectronic electrodes react adversely to such materials, reducing their beneficial properties.
Accordingly, it is recognized in the industry that an oxygen stable electrode is required for use with such HDC materials. Exotic materials such as noble metals (Pt, Rh) have been considered as the non-reactive electrode material. However, extravagant use of such materials as an electrode material is prohibitive due to their cost. Additionally, at least a 1200 angstroms (Å) conductive layer is required in order to form a suitable 3-D conductive pillar of 0.46 microns by 0.23 microns. Specifically for Pt, depositing such a conductive layer takes upwards of 15 minutes per wafer due to its very slow deposition rate using conventional deposition techniques. Such a long processing time per wafer is undesirable due to the increase in production expenses.
Accordingly, there is a need for a 3-D conductive pillar which is both suitable as an oxygen stable electrode for use with a HDC material and economical to produce.
SUMMARY OF THE INVENTION
The present invention provides an encapsulated 3-D conductive pillar and a method of formation thereof. Significant economic savings in material costs and production run times are achieved by filling a substantial portion of the volume of the pillar with a less expensive conductive material which can be deposited at a higher depositing rate. Additionally, the 3-D conductive pillar forms a suitable unreactive, oxygen-stable electrode for use with HDC materials as the encasing barrier layer metal provides a stable conductive interface between the HDC material and the encapsulated conductive material.
In accordance with one aspect of the invention provided in a first embodiment is a microelectronic structure comprising a substrate layer, a thin barrier layer metal on the substrate layer, and a conductive material encapsulated by the thin barrier layer metal. Provided in a second embodiment is a microelectronic capacitor comprising an insulating substrate layer having a conductive plug. The microelectronic capacitor further includes a thin barrier layer metal on the insulating substrate layer over the conductive plug, a conductive material encapsulated by the thin barrier layer metal, a dielectric layer provided over the barrier layer metal, and a top electrode layer provided over the dielectric layer. Provided in a third embodiment is a memory device having a microelectronic structure, the microelectronic structure comprising a substrate layer, a thin barrier layer metal on the substrate layer, and a conductive material encapsulated by the thin barrier layer metal. Provided in a fourth embodiment is a memory device having a capacitor, the capacitor comprising an insulating substrate layer having a conductive plug, a thin barrier layer metal on the insulating substrate layer over the conductive plug, a conductive material encapsulated by the thin barrier layer metal, a dielectric layer provided over the barrier layer metal, and a top electrode layer provided over the dielectric layer. Provided in a fifth embodiment is a computer system, the computer system includes a microelectronic device, the device comprises a substrate layer, a thin barrier layer metal on the substrate layer, and a conductive material encapsulated by the thin barrier layer metal. Provided in a sixth embodiment is a computer system, the computer system includes a microelectronic device, the device comprises an insulating substrate layer having a conductive plug, a thin barrier layer metal on the insulating substrate layer over the conductive plug, a conductive material encapsulated by the thin barrier layer metal, a dielectric layer provided over the barrier layer metal, and a top electrode layer provided over the dielectric layer.
In accordance with a second aspect of the present invention provided is a method of forming an encapsulated microelectronic structure suitable for use with a high-dielectric constant material. The method comprises providing a substrate layer, forming a container having a bottom and sidewalls from the substrate layer, and depositing a thin first layer of a barrier layer metal on the substrate layer covering at least the bottom and sidewall of the container. The method further comprises depositing a conductive material on the barrier layer metal substantially completely filling the container, depositing a thin second layer of the barrier layer metal on the conductive material to encapsulate the conductive material in the container, and planarizing the thin second layer of the barrier layer metal.
In accordance with the second aspect of the present invention provided is another method of forming an encapsulated microelectronic structure suitable for use with a high-dielectric constant material. The method comprises providing a substrate layer having a surface, forming a container having a bottom and sidewall from the substrate layer, and depositing a thin first layer of a barrier layer metal covering the bottom and sidewall of the container and the surface of the substrate. The method further includes depositing a conductive material covering the first layer of a barrier layer metal and completely filling the container, removing a portion of the conductive material to expose an upper portion of the barrier layer metal provided on the sidewall of the filled container, depositing a thin second layer of the barrier layer metal encapsulating the conductive material in the container, and planarizing the thin second layer of the barrier layer metal.
In accordance with the second aspect of the present invention provided is method of forming a capacitor having an encapsulated high-dielectric constant material. The method comprises providing a substrate layer having a conductive plug, and forming a container having a bottom and sidewall from the substrate layer, in which the conductive plug is located at the bottom of the container. The method further includes depositing a thin first layer of a barrier layer metal covering the bottom and sidewall of the container in which the conductive plug contacts the first layer of the barrier layer metal, depositing a conductive material substantially completely filling the container, and depositing a thin second layer of the barrier layer metal encapsulating the conductive material in the container. The method further includes planarizing the thin second layer of the barrier layer metal, forming a layer of a high-dielectric constant material over the conductive material, and, forming a top electrode over the high-dielectric constant material.
Other objects, features and advantages will appear more fully in the course of the following discussion.


REFERENCES:
patent: 4549927 (1985-10-01), Goth et al.
patent: 4866008 (1989-09-01), Brighton et al.
patent: 5008730 (1991-04-01), Huang et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5581436 (1996-12-01), Summerfelt et al.
patent: 6034389 (2000-03-01), Burns, Jr. et al.
patent: 6046108 (2000-04-01), Liu et al.
patent: 6054331 (2000-04-01), Woo et al.
patent: 6114238 (2000-09-01), Liao
patent: 6114243 (2000-09-01), Gupta et al.
patent: 6130124 (2000-10-01), Lee
patent: 6168991 (2001-01-01), Choi et al.
patent: 6274499 (2001-08-01), Gupta et al.
patent: 6291082 (2001-09-01), Lopatin
patent: 6320213 (2001-11-01), Kir

Affiliated with

Also associated with

Rating

Method of forming an encapsulated conductive pillar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming an encapsulated conductive pillar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming an encapsulated conductive pillar will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3051083