Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1999-03-31
2000-04-11
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438584, H01L 213205
Patent
active
060487836
ABSTRACT:
A double-layered electrode layer is formed on a substrate according to a process in which lower and upper electrode layer forming materials are deposited on a substrate in this order, then a lower photoresist pattern is formed on the upper electrode layer forming material. Next, the lower and upper electrode layer forming materials are isotropically etched to obtain lower and upper electrode layers, after which the upper electrode layer is anisotropically etched such that a width of the upper electrode layer becomes less than that of the lower electrode layer.
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patent: 5147814 (1992-09-01), Takeuchi
patent: 5821159 (1998-10-01), Ukita
Kim Hye-Young
Moon Kyo-Hoo
Bowers Charles
Hawranek Scott J.
LG. LCD Inc.
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