Method of forming an electrical via structure

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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Details

156644, 156655, 156656, 1566611, 156668, 156901, 430313, 430317, 430318, B44C 122, B29C 3700, C23F 102, C03C 1500

Patent

active

050340913

ABSTRACT:
A via (26) is formed through a dielectric layer (8) separating two conductive layers (16,28) by establishing a laterally erodible mask (18) over the dielectric (8), with a window (24) over the desired via location. The mask (18) and exposed dielectric material (8) are eroded simultaneously, preferably by reactive ion etching, producing a via (26) through the dielectric (8) which expands laterally as vertical erosion proceeds. The erosion conditions, the materials for the mask (18) and dielectric (8), and the initial window (24) taper are selected so that the final via (26) is tapered at an angle of less than about 45.degree. to the lower metal layer (6), and preferably about 30.degree.-45.degree., to enable a generally uniform width for the upper metallization (28) in the via (26). A non-erodible mask (10) is established over the dielectric layer (8) lateral to the via (26) during fabrication to prevent the propagation of pinhole defects from the erodible mask (18) into the dielectric (8), and is normally removed prior to completing the structure.

REFERENCES:
patent: 3986912 (1976-10-01), Alcorn et al.
patent: 4426249 (1984-01-01), Brown et al.
patent: 4461672 (1984-07-01), Musser
patent: 4484978 (1985-11-01), Keyser
patent: 4631248 (1986-12-01), Pasch
patent: 4645562 (1987-02-01), Liao et al.
patent: 4806199 (1989-02-01), Gualandris
patent: 4816115 (1989-03-01), Horner et al.
A Planar Approach to High Density Copper-Polyimide Interconnect Fabrication, by J. Tony Pan, Steve Poon, Brad Nelson, pp. 90-106.

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