Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-10
2001-03-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S648000, C438S649000, C438S653000, C438S660000, C438S664000, C438S685000
Reexamination Certificate
active
06200895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates in part to the formation of shallow junctions in semiconductor devices. The present invention also relates to high aspect-ratio contacts and methods of forming the same in semiconductor devices. In particular, the present invention relates to formation of contacts with refractory metal and refractory metal nitride liners that assist in filling of the contacts, which contacts are incorporated in a circuit with semiconductor devices. Additionally disclosed is the combination of shallow junction formation and high aspect-ratio contacts that form interconnects between a shallow junction and semiconductor device wiring. More particularly the present invention relates to metal filled contacts that fill contact holes in semiconductor devices that are initially lined with a titanium layer and at least one other layer. Other preferred layers for lining the contact holes include titanium nitride, cobalt, germanium, and silicon.
2. The Relevant Technology
The process of miniaturization has the goal of increasing the density of the count of semiconductor devices in a given unit area. Miniaturization requires reducing the size, both lateral and vertical, of semiconductor devices and placing them closer to neighboring semiconductor devices.
Shallow junction structures have the advantage of forming faster devices, including faster on-off times and better control of gate lengths because gate lengths are of dimensions that are less than a quarter micron. Shallow junctions are defined as anything less than about 0.2 microns deep and where doping of the junction is in a concentration range of less than 10
19
atoms/cm
3
. At these minute dimensions, device leakage can become a disabling factor for such structures. Leakage in the pico amp range at these dimensions is detrimental in memory devices. For static random access memories (SRAMS) and logic devices on the other hand, charge leakage above the pico amp range can be tolerated.
In the formation of shallow junctions, detrimental charge leakage has the effect of not being able to turn off the device. For example, where a shallow junction is 0.15 microns deep and titanium silicide penetration into the active area is about 900 Å, charge leakage in the remaining unconsumed area of the active area is a substantial portion of the total charge that passes therethrough. This causes the problem of not being able to turn off the device.
Process control at these dimensions with titanium silicide formation also is problematic in that controlling titanium silicide encroachment into the shallow junction requires extra time, expense, and optimization that may be uneconomical for specific applications. Another difficulty with titanium and shallow junctions is due to the extreme thinness of titanium layers required for shallow junctions as defined above. A requisite titanium layer thickness can be easily penetrated and an aluminum silicide spike can form in the active area that disables the specific device by shorting out the active area. Titanium silicide also has a high surface tension associated with it compared to the silicon in active areas that causes spalling off from semiconductor substrate active areas and agglomeration with contact corridor walls.
Another difficulty in the process of miniaturization is forming contacts in ever-decreasing dimensions. For example, the aspect ratio of a contact as illustrated in
FIG. 1
, is defined as the height Y of the contact corridor divided by the width X. With ever-decreasing contact sizes, higher aspect ratios must be achieved. A high aspect ratio contact, for example, an aspect ratio of about
8
:
1
presents a difficulty for the microchip fabricator in miniaturization. Difficulties have been encountered in depositing aluminum lines and contacts by conventional sputtering processes when submicron high aspect ratio recesses are to be filled. As the openings become smaller and deeper, the bottom and sides of an opening receive fewer deposited metal ions than the top surface of the opening, with the result that the metal layer hangs over the opening, called “breadloafing.” Thus over time, the bottom and sides of the opening receive inadequate amounts of metal and bread-loafing closes the opening before the opening is filled.
While the aluminum in the contact or metal line and the silicon in the semiconductor substrate active area must be electrically connected, it has become useful to use intermediate layers to provide better electrical connection to the silicon and to provide an electrical junction, while at the same time to provide a metallurgical barrier between silicon and aluminum to prevent spiking of the aluminum into the silicon. Spiking can interfere with the performance and reliability of the integrated circuit.
Conventionally, one method which has been used to accomplish the metallurgical barrier has been to form a layer of titanium over a semiconductor substrate at the contact exposed site to form a titanium silicide junction at the exposed site, and to form a titanium nitride layer elsewhere in that the titanium layer is formed in the presence of nitrogen. While this method accomplishes the metallurgical barrier by the formation of the titanium silicide junction, it often is inadequate to form the titanium nitride layer has a barrier because of the competing simultaneous formation of titanium silicide and titanium nitride at the titanium region that covers the exposed semiconductor substrate site. Titanium silicide also has the problem, as stated above, of imposing undesirable stresses between the titanium layer as formed upon the active area and the silicon material of which the active area is composed. As a balance is attempted to be struck between depositing a thin enough titanium layer that will not substantially consume the shallow junction active area, and sufficient titanium so as to not spall off from the active area, the ever-increasing pressure of miniaturization has caused a heightened interest in seeking an alternative method of forming the metallurgical barrier that serves simultaneously as an electric junction.
One prior art solution to this inadequate prior art method has been to form the titanium silicide barrier layer first and then to sputter additional titanium nitride over the titanium silicide or titanium silicide/titanium nitride layer. In this way, a sufficient thickness of titanium nitride may be formed to provide a desired thickness in a barrier layer.
Sputtered layers of titanium nitride have been used in integrated circuits as barrier layers for recesses such as contact holes, vias, and trenches. Sputter-deposited titanium nitride in a high aspect ratio contact, however, is not desirably conformal and the step coverage thereof within high aspect ratio recesses is poor. The result is an unacceptably thin or discontinuous titanium nitride barrier layer that lines the walls of the high aspect ratio contact.
As aspect ratios in recesses have increased, the need to get the sputtered aluminum metallization to substantially fill the recess has proved inadequate in spite of improved titanium nitride barrier layers. High pressure and/or temperature aluminum recess-filling techniques have been developed, but with ever-increasing pressure to miniaturize, filled recesses with aspect ratios that exceed 8:1 have been difficult or impossible to achieve.
It has been proposed to form the titanium nitride layer in a recess by chemical vapor deposition (CVD), for example by using titanium tetrachloride (TiCl
4
) in the presence of NH
3
, H
2
and Ar. Although the TiCl
4
CVD process has improved reflow techniques, substantially filled recesses with aspect ratios greater than about 5:1 have been elusive. One problem that has been realized is that aluminum reflow requires a substantially pristine refractory metal nitride surface, whereas interstitial titanium nitride layer impurities incident to the TiCl
4
CVD process cause the aluminum to become contaminated and to lose its relatively low-friction fl
Givens John H.
McTeer E. Allen
Micro)n Technology, Inc.
Nguyen Ha Tran
Niebling John F.
Workman & Nydegger & Seeley
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