Method of forming an arsenic silicon glass film onto a...

Details Method of forming an arsenic silicon glass film onto a... Method of forming an arsenic silicon glass film onto a...

1999-07-28

2001-04-17

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C427S070000

Reexamination Certificate

active

06218319

ABSTRACT:

FIELD OF INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to an improved method of forming an arsenic silicon glass (ASG) film having an uniform thickness onto a silicon structure. The method finds a very useful application in the conformal deposition of such an ASG film in deep trenches formed in a silicon substrate to provide the necessary doping to create the buried plate region of cell capacitors. Deep trench cell capacitors are extensively employed in EDO (extended data out) and SDRAM (synchronous dynamic random access memory) memory chips. This process improvement significantly reduces chip manufacturing costs.
BACKGROUND OF THE INVENTION
To date, deep trenches are extensively used in the manufacture of integrated circuits (ICs) and in particular in the manufacture of 64 and 256 Mb and will be probably used up to 1 Gb EDO and SDRAM memory chips in the future to define the storage capacitor of each memory cell. Basically, a deep trench is formed in a slightly doped silicon substrate, then a thin dielectric film is conformally deposited thereon to coat the entire interior trench surface and finally, the trench is filled with doped polysilicon. This silicon substrate/dielectric film/doped polysilicon composite structure forms the cell capacitor. To keep an acceptable capacitor value in spite of continuous size reduction, the thickness of the dielectric film is constantly reduced. In turn, the voltage across the dielectric film must be drastically reduced to avoid undesired voltage breakdown effects. In order to achieve this voltage reduction, a doped area is created in the silicon substrate around the bottom of the cell capacitor. This area is commonly referred to as the “buried plate” (BP) region in the technical literature. To that end, an arsenic silicon glass (ASG) film is conformally deposited onto the chip surface to coat the trench side wall and will be subsequently used to generate the arsenic (As) atoms to heavily dope the silicon substrate in order to create these BP regions. Then, after several processing steps which are necessary to set the buried plate region depth from the top trench surface, the As atoms are out diffused from the ASG film into the silicon substrate during an anneal. A conventional buried plate region formation process specifically includes the eight basic steps recited below.
1—Etching deep trenches in a p-type silicon substrate coated with a patterned pad stack comprised of a bottom silicon oxide (SiO2) layer and a top silicon nitride (Si3N4) layer as standard.
2—Depositing a conformal ASG film onto the structure to coat deep trench side walls.
3—Filling the deep trenches with a planarizing medium such as a photoresist.
4—Removing the photoresist down to a given depth into deep trenches.
5—Removing the ASG material from unprotected areas.
6—Stripping the photoresist material remaining into deep trenches and then, depositing a conformal SiO2 layer onto the structure.
7—Out diffusing arsenic atoms from the ASG film into the silicon substrate.
8—Finally, removing SiO2 and ASG materials from deep trench side walls.
FIG. 1A
schematically illustrates the starting structure
10
consisting of a p-type silicon substrate
11
with a 10 nm thick silicon oxide layer
12
and a 220 nm thick silicon nitride layer
13
formed thereon. These two layers will be referenced to hereinbelow as the SiO2/Si3N4 pad layer
12
/
13
. As apparent in
FIG. 1A
, a deep trench referenced
14
has been formed in the substrate
11
by RIE etching as standard. Typically, deep trench
14
has a depth of about 7 &mgr;m and an oblong section of about 550×320 nm at the substrate surface.
Now, turning to
FIG. 1B
, an arsenic silicon glass (ASG) is conformally deposited by LPCVD to coat the interior trench side wall with a 45 nm thick film referenced
15
. As known for those skilled in the art, As atoms contained in ASG film
15
will subsequently act as N type dopants. This step is performed in a deposition equipment such as a vertical hot dual wall SVG 7000+LPCVD reactor manufactured and sold by SVG THERMCO, Orange, Calif., USA, schematically illustrated in
FIG. 3
that will be detailed later on. The reactive atmosphere includes tetraethylorthosilicate (TEOS) and triethylarsenate (TEASAT) gases.
Then, a 1.8 &mgr;m thick layer of a planarizing medium, typically a photoresist, is conformally deposited onto the structure in order to fill the deep trench
14
in excess. A photoresist such as AZ7511 manufactured by CLARIANT, Brunswick, N.J., USA, is adequate in that respect. As shown in
FIG. 1C
, after reflow, the photoresist layer bearing numeral
16
has a planar surface.
After photoresist reflow was performed, a given amount of the photoresist material is removed by a conventional lithographic process, so that the surface of photoresist layer
16
stands at about 1.5 &mgr;m below the structure surface. The remaining material of photoresist layer
16
exhibits a typical recessed shape at its upper surface in trench
14
as shown in FIG.
1
D.
Now, the unprotected portions of the N+ doped ASG film
15
are removed by wet etching in a buffered HF bath. An overetching occurs during this wet etch step at the top annular portion of the ASG film
15
to produce the moat or dip out
17
, as apparent in FIG.
1
E.
Next, the photoresist material remaining at the bottom of deep trench
14
is stripped by wet etching in a Huang SP solution and a 25 nm thick SiO2 layer
18
is conformally deposited by PECVD onto the structure to coat the deep trench side wall. An AME 5000 tool commercially available from Applied Materials Inc., Santa Clara, Calif., USA is appropriate. After these two process steps have been performed, the structure
10
is shown in FIG.
1
F.
The structure
10
is then heated to diffuse the As doping atoms trapped in the ASG film
15
into the adjacent portions of the silicon substrate
11
to create the buried plate region
19
. At this stage of the BP region formation process, the structure
10
is shown in FIG.
1
G.
After the As dopant out diffusion step is achieved by adequate annealing conditions in the SVG 7000+ reactor to reach the desired junction (or diffusion) depth of at least 0.25 &mgr;m. The ASG film
15
and the SiO2 layer
18
are removed by means of an appropriate wet etching. This last step ends the buried plate region formation process and the final structure is shown in FIG.
1
H. Any attempt to create buried plate region
19
by mean of an arsenic ion implantation step would fail because the deep trench is too minute and such implantation would require an inaccessible level of implant energy.
To understand the specific buried plate region process requirements, it is necessary to consider the structure
10
at a much further stage of the chip fabrication process.
FIG. 2
shows structure
10
after gate conductor stack and source/drain regions completion. At this stage, with regard to the structure depicted in
FIG. 1H
, the SiO2/Si3N4 pad layer
12
/
13
has been eliminated and the trench
14
has been filled with doped polysilicon to form the first electrode of the cell capacitor. The polysilicon fill is electrically isolated from the substrate
11
by a 30 nm thick TEOS SiO2 collar layer
21
on its upper part and a 5 nm thick reoxidized silicon nitride layer
22
on its lower part. The latter layer forms the dielectric film of the cell capacitor. Still very schematically, two ion implantation steps are performed to define first a 1000 nm thick N-well
23
, then a 800 nm thick P-well region
24
. The second electrode of the cell capacitor is thus formed by the buried plate region
19
, the N-well region
23
being used to interconnect all the buried plate regions of the chip. Finally, after gate conductor stack
25
and source/drain regions
26
formation, an IGFET bearing numeral
27
visible in
FIG. 2
is created.
It is essential to chip reliability that the top of BP region
19
is located below and preferably at about 450 nm from the P-well/N-well

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