Semiconductor device manufacturing: process – Direct application of electrical current – To alter conductivity of fuse or antifuse element
Reexamination Certificate
2000-08-01
2002-09-03
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Direct application of electrical current
To alter conductivity of fuse or antifuse element
C438S132000, C438S601000
Reexamination Certificate
active
06444544
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method used to retard corrosion of copper structures resulting from a laser write procedure, performed to an adjacent copper fuse element
(2) Description of Prior Art
Fuse elements have been used to allow defective regions, such as a defective gate array located in a body gate arrays, to be deleted, and sometimes replaced by another non-defective gate array. This is accomplished via use of fuse elements, placed between specific gate arrays, allowing defective regions to be removed from the main body of gate array regions, by ‘blowing’ of, or opening of, the fuse element. This results in physical, as well as electrical discontinuity of the defective gate array region, in regards to the main body of devices. The use of copper for metal interconnect, and for metal via plug structures, conveniently allow the fuse element to also be fabricated from a copper layer. However the laser writing, or the procedure use to open or blow the copper fuse element, can result in degradation to the adjacent copper structures, in terms of oxidation or corrosion. The laser writing procedure produces oxygen, water, and fluorine ions, which will corrode, as well as oxidize the copper interconnect structure of nearby gate array elements, resulting in yield loss due to the reduced conductivity of the oxidized copper structures. The oxidation and corrosion phenomena can also impact reliability of the structures, in regards to electromigration. In addition the oxygen, water, and fluorine ions, incorporated in the copper interconnect structures, can during subsequent temperature excursions propagate and extend into the low resistivity copper interconnects, resulting in extensive conductivity, and performance, decreases.
This invention will describe a process, and structure, in which an aluminum guard structure is formed at a location in the copper interconnect structure that will prevent propagation of the corrosive effect of the laser writing from deleteriously influencing the copper interconnect structures. Prior art, such as Liaw, in U.S. Pat. No. 5,970,346, as well as Lien et al, in U.S. Pat. No. 6,008,075, describe guard rings, and metal guard spacers, near the fuse structure, but these prior arts do not show the concept or details of the present invention, featuring the fabrication and placement of a corrosion retarding aluminum guard structure, in a copper interconnect structure, in a region adjacent to the copper fuse element.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a copper fuse element, located between bodies of array devices, comprised with copper interconnect, back end of line, (BEOL), wiring.
It is another object of this invention to integrate the fabrication of an aluminum guard structure, placed adjacent to the copper fuse element, with the fabrication sequence used for copper BEOL interconnect structure.
It is still another object of this invention to form the aluminum guard structure in each body of gate arrays, or device elements, with each aluminum guard structure located as part of an upper level of a copper interconnect structure, adjacent to the copper fuse element.
In accordance with the present invention a method of forming an aluminum guard structure, as part of a copper interconnect, to retard the oxidation and corrosion effects of a laser write procedure, performed to an adjacent copper fuse element, is described. Multi-level, metal interconnect structures, comprised of levels of copper interconnect shapes, and copper plug structures, are formed in insulator layers, electrically and physically connecting underlying device regions in a semiconductor substrate, to a subsequent wire bond, or flip chip pad. Specific multi-level metal interconnect structures are used for communication to specific arrays of devices. During the fabrication of the multi-level metal interconnect structures a copper fuse element is simultaneously formed, physically and electrically connecting a first multi-level metal interconnect structure to a main body of arrays, via connection to second multi-level metal interconnect structure. In addition a protection ring, comprised of copper interconnect, and plug shapes, is simultaneously fabricated during formation of the multi-level copper interconnect structures. Patterning procedures are then employed to form a laser write via hole in a top portion of an insulator layer, resulting in a bottom portion of the insulator layer directly overlying the copper fuse element. The same patterning procedure is used to form a guard structure opening in the insulator layer, and in an each multi-level copper interconnect structure. Deposition of an aluminum layer and subsequent patterning procedures, result in the formation of aluminum guard structures, located as part of the multi-level copper interconnect structures, located near the copper fuse element, used to prevent oxidation and corrosion of the multi-level copper interconnect structures, during a laser write procedure applied to the copper fuse element performed in the laser write via hole..
REFERENCES:
patent: 5926697 (1999-07-01), Yaung et al.
patent: 5970346 (1999-10-01), Liaw
patent: 6008075 (1999-12-01), Lieu
patent: 6294474 (2001-09-01), Tzeng et al.
Hu Chu-Wei
Lin Chung-Te
Lin Hsien-Chin
Pan Kuo-Hua
Ackerman Stephen B.
Everhart Caridad
Lee Calvin
Saile George O.
Taiwan Semiconductor Manufacturing Company
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