Method of forming an alignment key on a semiconductor wafer

Details Method of forming an alignment key on a semiconductor wafer Method of forming an alignment key on a semiconductor wafer

2001-02-23

2003-12-16

Graybill, David E. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S620000, C257S618000, C438S462000, C438S401000, C361S741000, C361S802000

Reexamination Certificate

active

06664650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices and, more particularly, to a method of forming an alignment key on a semiconductor wafer.
2. Description of the Related Art
Semiconductor integrated circuit devices are made by forming a plurality of features in layers on a semiconductor wafer. The wafer is typically made from silicon or gallium arsenide, and photolithographic techniques are commonly used to form the features on the wafer. Each feature, when formed, must be aligned with the previously formed features in order for the integrated circuit to be properly constructed. To achieve this alignment, the usual practice is to provide alignment keys on the semiconductor wafer and corresponding alignment keys on each of the photolithographic masks used to form the features on the wafer. When the keys on the mask are aligned with the keys on the wafer, the features to be formed by the particular mask will be aligned with the features previously formed on the wafer.
FIG. 1
shows a semiconductor wafer
1
with integrated circuits formed on the wafer. The wafer
1
contains numerous die (or chip) areas
2
in which the integrated circuits are formed. The die areas
2
formed on the wafer
1
are separated from each other by vertical and horizontal scribe lines
3
. As shown in
FIG. 1
, the horizontal scribe lines are evenly spaced and parallel to each other, the vertical scribe lines are evenly spaced and parallel to each other, and the horizontal and vertical scribe lines intersect at substantially right angles. After the wafer
1
has been processed to form the integrated circuits on each die area
2
, the wafer
1
is cut into individual integrated circuit die by cutting along the scribe lines
3
.
The conventional method of forming alignment keys on a semiconductor wafer will now be described with reference to FIG.
2
. The alignment keys are formed on the scribe line areas at selected times during the fabrication process of the integrated circuit devices. As the fabrication process proceeds, the layer of material
13
formed on the surface of the semiconductor wafer substrate
10
increases in thickness. An alignment key
11
is formed by etching the layer
13
to produce channels in layer
13
. After formation of the alignment key
11
, a photoresist layer
12
is deposited over the entire surface of the semiconductor substrate
10
. However, because of the thickness of the layer
13
and the resulting large depth of the channels forming the alignment key
11
, the deposited photoresist layer
12
is often irregular and provides poor coverage of the channels, as shown in FIG.
2
. This poor photoresist coverage of the alignment key
11
influences the die areas adjacent to the scribe line and may cause an undesireable “speed-boat” phenomenon.
This problem becomes more severe as more integrated circuit dies are packed more densely onto the wafer and the scribe lines are made narrower so that they occupy less area. This reduced width of the scribe lines also reduces the width of the channels forming the alignment keys and exacerbates the problem of poor photoresist coverage.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming or at least reducing the effects of the problems set forth above.
One feature of the invention is that the alignment keys are formed with channels having a reduced depth. Another feature of the invention is the use of a layer of material to block the etch of the alignment keys so the alignment key channels extend down only as for as that layer. This blocking layer is preferably formed by depositing a layer of material and etching the layer so that a portion of the layer remains on the scribe lines at the locations where the alignment keys will be formed. The blocking layer is preferably the layer which deposited in the step just preceding the formation of the alignment keys. The blocking layer preferably has etch selectivity with respect to the material in which the alignment keys are etched. Preferably, the blocking layer is any conductive layer composing the integrated circuit devices and the alignment key is etched into an insulating layer.
In accordance with one aspect of the invention there is provided a method for forming an alignment key on a semiconductor wafer having intersecting scribe line areas thereon to define a plurality of integrated circuit areas, the method comprising the steps of depositing a plurality of layers on the integrated circuit areas, depositing a predetermined one of the layers on one or more of the scribe line areas, and forming the alignment key on the predetermined layer. The step of forming the alignment key may comprise the steps of depositing an additional layer of material on the predetermined layer, and etching the additional layer down to the predetermined layer to form the alignment key.
In accordance with another aspect of the invention there is provided a semiconductor wafer comprising a plurality of scribe line areas defining a plurality of integrated circuit areas on the semiconductor wafer, a plurality of layers formed on the integrated circuit areas, a predetermined one of the layers formed on one of the scribe line areas, and an alignment key formed on one of the scribe line areas, the alignment key having channels extending down to the predetermined layer.


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