Method of forming a via hole filled with a conducting material,

Details Method of forming a via hole filled with a conducting material, Method of forming a via hole filled with a conducting material,

1997-12-09

1999-11-16

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438622, 438637, 438624, 438970, 148DIG133, H01L 213205, H01L 214763

Patent

active

059857455

ABSTRACT:
A semiconductor device fabricating method is capable of securing an increased margin for absorbing an error in aligning a viahole with an underlying wiring layer when forming a viahole in a layer insulating film to connect an upper wiring layer overlying the layer insulating film and a lower wiring layer underlying the layer insulating film to enable the miniaturization of a pattern and the miniaturization of the semiconductor device. The semiconductor device fabricating method forms a first Si.sub.3 N.sub.4 film between a first wiring layer and a second wiring layer, and a second layer insulating film, a third layer insulating film and a fourth layer insulating film all of SiO.sub.2 over the second wiring layer. When forming a third viahole through the layer insulating films so as to reach the second wiring layer, the layer insulating films are etched in a high SiO.sub.2 /Si.sub.3 N.sub.4 selectivity of about twenty. The etching process for forming the third viahole can be terminated on the second wiring layer and the first Si.sub.3 N.sub.4 film even if the position of the third viahole is dislocated slightly relative to the second wiring layer.

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