Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-05-03
2003-06-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S296000, C438S404000
Reexamination Certificate
active
06583025
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming isolated trenches in a semiconductor substrate.
This is a counterpart of, and claims priority to, Korean Patent Application No. 2000-39323, filed Jul. 10, 2000, and Korean Patent Application No. 2000-69980, filed Nov. 23, 2000, the contents of each of which are incorporated herein by reference in their entirety.
2. Description of the Related Art
In a conventional semiconductor manufacturing process referred to as a trench isolation process, a semiconductor substrate is etched to form a series of trenches, the trenches are filled with an insulating material, and then the insulating material is planarized to form an insulating layer. Because the substrate itself is directly etched to form the trench, stress is produced along an inner wall of the substrate defining the trench, thereby producing defects in the substrate. An oxide liner and a nitride liner are formed on the inner wall defining the trench to alleviate such stress. The nitride liner, however, is over-etched during a subsequent process, whereby a so-called dent phenomenon occurs at an edge of a trench isolation layer.
FIG. 1
illustrates such a problem in a conventional trench isolation structure. A substrate
10
is etched to form a trench therein. A silicon nitride layer is conventionally used as an etching mask in the etching process for forming the trench. An oxide liner
12
and a nitride liner
13
are sequentially formed on an inner wall of the semiconductor substrate
10
defining the trench. An insulating layer
15
is then formed in trench. Next, the etching mask is removed using a wet etching process. Unfortunately, the nitride liner
13
on a sidewall of the trench is also etched while the etching mask is being removed. Therefore, an edge of the trench isolation structure becomes indented, i.e., the so-called dent phenomenon occurs in the region designated by reference numeral
17
. If a gate pattern of a transistor is formed at the indented region, the intensity of the electric field spikes at that region and the threshold voltage of the transistor is lowered accordingly.
The dent phenomenon
17
is alleviated somewhat by a densifying process performed mainly for reducing the rate at which the insulating material can be etched. The densifying process comprises annealing the insulating layer
15
. The annealing process for densifying the insulating layer
15
also densities the nitride liner
13
, whereby the etching-tolerance of the nitride liner
13
is enhanced. The annealing process is performed at a high temperature of 1000-1150° C. in a nitrogen ambient. However, such a high temperature annealing process creates stress between the insulating layer
15
and the semiconductor substrate
10
. The stress is known to facilitate the occurrence of slip or leakage current which degrades the performance of the final device. Accordingly, the recent trend is toward the use of a low temperature annealing process, specifically a nitrogen annealing process or a wet annealing process. The nitrogen annealing process is carried out at a temperature of 700-900° C. in a nitrogen ambient, whereas the wet annealing process is carried out at a temperature of 700-900° C. in a vapor ambient.
Unfortunately, the low temperature annealing process does not densify the nitride liner sufficiently to prevent a significant dent phenomenon from occurring.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method of forming a trench isolation structure which prevents a nitride liner serving as an oxidation barrier layer from being over-etched during an etching process performed after the nitride layer has been formed.
To achieve this object, the present invention provides a trench isolation method in which the oxidation barrier layer is specifically densified in a furnace before the etching process is conducted. First, a trench is formed in a semiconductor substrate. Then the oxidation barrier layer is formed on an inner wall of the substrate that defines the trench. The oxidation barrier layer is annealed in a furnace in a process that densities the layer completely. Once the oxidation barrier layer is densified, an insulating layer is formed on the oxidation barrier layer to fill the trench.
The trench is formed as follows. A pad oxide layer and an etch-stop layer are sequentially formed on the substrate. Preferably, the etch-stop layer is made of silicon nitride. The pad oxide layer and the etch-stop layer are then patterned such that a predetermined area of the substrate is exposed. The substrate is then etched using the etching mask pattern as an etching mask, to form the trench.
The oxidation barrier layer is made of silicon nitride. Preferably, the annealing process is carried out at a temperature of 1000° C. or more in a nitrogen ambient. Alternatively, the annealing process may be carried out at a temperature of 800° C. or more in an oxygen and vapor ambient.
Further, an oxide liner is formed between the inner wall that defines the trench and the oxidation barrier layer. Preferably, a capping oxide layer is additionally formed between the oxidation barrier layer and the insulating layer.
Insulating material is then deposited on the structure and is then planarized to form the insulating layer in the trench.
Subsequently, the etching mask pattern is etched away. Regardless, the oxidation barrier layer is not over-etched by this process because it has been densified.
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Rocchegiani Renzo N.
Samsung Electronics Co,. Ltd.
Smith Matthew
Volentine & Francos, PLLC
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