Method of forming a thin film transistor

Details Method of forming a thin film transistor Method of forming a thin film transistor

2003-03-24

2004-08-10

Pham, Hoai (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S151000, C438S166000

Reexamination Certificate

active

06773969

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of forming a thin film transistor (TFT) of an organic light-emitting diode (OLED) display, and more specifically, to a method of forming a TFT comprising a crystalline silicon layer.
2. Description of the Prior Art
In various types of flat panel displays, since an organic light-emitting diode (OLED) display has many beneficial characteristics, such as having a spontaneous light source, a wide viewing angle, highresponse velocity, low power consumption, full-color, simpler structure, and a wide operating temperature, the OLED display has been used extensively in small and medium scale portable display fields.
Please refer to
FIG.1
to
FIG.4
of schematic views of forming a thin film transistor (TFT) of an OLED display according to the prior art. As shown in
FIG.1
, a gate
12
, composed of copper (Cu), is formed on a substrate
10
. By performing a plasma enhanced chemical vapor deposition (PECVD).process, a gate insulating (GI) layer
14
, comprising silicon oxide (SiO
x
), silicon nitride (SiN
y
) orsilicon oxynitride (SiON), is formed on the gate
12
. An amorphous silicon layer
16
and a dopedn
+
layer
18
are then sequentially formed on the GI layer
14
.
As shown in
FIG. 2
, by performing a first photo-etching-process (PEP), portions of the dopedn
+
layer
18
and the amorphous silicon layer
16
are removed. Then, an indium tin oxide (ITO) layer
20
is formed on the substrate
10
, and a second PEP is performed to remove portions of the ITO layer
20
. As shown in
FIG. 3
, a metal layer
22
, comprising tungsten (W), chromium (Cr), copper (Cu) or Molybdenum (Mo), is formed on the substrate
10
, and a third PEP is performed to remove portions of the metal layer
22
and the dopedn
+
layer
18
to simultaneously form a source
24
and a drain
26
of the TFT on the substrate
10
and expose portions of the amorphous silicon layer
16
thereafter.
Finally, as shown in
FIG. 4
, a passivation layer
28
, comprising silicon oxide or silicon nitride, is formed on the substrate
10
, and a fourth PEP is performed to remove portions of the passivation layer
28
so as to finish the fabrication of the TFT of the OLED display according to the prior art.
However, the amorphous silicon layer
16
is composed of silicon molecules not crystallized and comprises numerous Si—H bonds and silicon dangling bonds. Therefore, mobility of electrons in the amorphous silicon layer
16
is reduced, causing electrons trapped in the amorphous silicon layer
16
and further penetrate into the GI layer
14
under a long-time operation of the TFT. As a result, a voltage stress on the TFT is generated, leading to an increased threshold voltage (v
th
) and a reduced turn on current (I
on
) of the TFT that seriously downgrade the display quality of the OLED display.
SUMMARY OF INVENTION
It is therefore a primary object of the present invention to provide a method of forming a thin film transistor (TFT) of an organic light-emitting diode (OLDE) display so as to prevent an increased threshold voltage (V
th
) and a reduced turn on current (I
on
) of the TFT that seriously downgrade the display quality of the OLED display.
According to the claimed Invention, the TFT is formed on a substrate. At the beginning of the invention, a first metal layer Is deposited on the substrate, and a first photo-etching-process (PEP) is then performed on the first metal layer to form a gate of the TFT on the substrate. A gate insulating (GI) layer and a first amorphous silicon layer is sequentially formed on the gate thereafter. By performing a dehydrogen treatment, hydrogen atoms in the first amorphous silicon layer is removed. A re-crystallizing process is then performed to transfer the first amorphous silicon layer into a crystalline silicon layer, and a second amorphous silicon layer and a dopedn
+
layer are sequentially formed on the gate thereafter. By performing a second PEP, portions of the dopedn
+
layer, the second amorphous silicon layer and the crystalline silicon layer are removed. Then, a second metal layer is formed on the substrate, and a third PEP is performed to form a source and a drain of the TFT and to simultaneously remove portions of the dopedn
+
layer to expose portions of the second amorphous silicon layer. Finally, a passivation layer is formed to cover the source and the drain.
It is an advantage of the present invention against the prior art that the dehydrogen treatment is performed to remove hydrogen atoms in the first amorphous silicon layer, and the re-crystallizing process is then performed to transfer the first amorphous silicon layer into the crystalline silicon layer. Then, the Si-H bonds and silicon dangling bonds in the crystalline silicon layer are erased, and the grain sizes of silicon molecules in the crystalline silicon layer are increased. Mobility of electrons in the crystalline silicon layer is therefore improved, preventing electrons from being trapped in the crystalline silicon layer and further penetrating into the GI layer. As a result, an increased threshold voltage (V
th
) of the TFT caused by voltage stress are prevented, even under a long-time operation of the TFT. Consequently, a constant turn on current (I
on
) of the TFT is assured, leading to a stable display quality of the OLED display.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.


REFERENCES:
patent: 6504175 (2003-01-01), Mei et al.

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