Method of forming a test key architecture

Details Method of forming a test key architecture Method of forming a test key architecture

1999-05-21

2000-10-17

Chaudhari, Chandra

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438238, H01L 2166

Patent

active

061330558

ABSTRACT:
A method of forming a test key architecture on a silicon wafer. The method includes forming trench isolation regions between a source region and a drain region. Thereafter, a plurality of active regions are formed in parallel above the trench isolation regions such that the smallest possible width for each active region is chosen to reduce overall area occupation and increase the number of test keys. Next, a long pass gate is formed above the trench isolation regions, crossing and covering the parallel-connected active regions. Consequently, the effect due to stress-induced defect and the probability of leakage current due to parasitic device effect are greatly increased.

REFERENCES:
patent: 5426065 (1995-06-01), Chan et al.
patent: 5773317 (1998-06-01), Wu et al.
patent: 5976901 (1999-11-01), Igel

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