Method of forming a substrate contact in a field effect...

Details Method of forming a substrate contact in a field effect... Method of forming a substrate contact in a field effect...

2001-05-03

2004-04-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S299000, C438S303000, C438S305000, C438S586000, C438S595000

Reexamination Certificate

active

06720242

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a field effect transistor (FET) on a substrate having a buried insulator layer, such as silicon on insulator (SOI), and, in particular, to an improved method of forming a front side substrate contact for the FET device.
2. Description of the Related Art
The ever increasing demand for high speed integrated circuits has had a significant impact on the development of integrated circuits formed on an insulating substrate, such as SOI devices, due to their superior features with respect to reduced parasitic capacitance of the active transistor region and improved latch-up immunity. In an FET formed on a substrate having an insulating layer formed thereon, also referred to as a buried oxide layer when an SOI device is considered, a substrate contact is required for removing charge carriers that would otherwise accumulate below the channel region of the FET. For example, in an NMOS device, the drain diode is usually biased in the reverse direction, wherein the bias voltage often exceeds a voltage level sufficient to initiate a weak Avalanche breakdown. Accordingly, electron-hole pairs are generated in the drain region. Consequently, while the electrons drift away with the drain current, the holes float into the well and finally accumulate at the buried oxide layer. Charge carriers accumulated under the channel region, however, will significantly affect the electrical characteristics of the transistor device, such as gate threshold voltage, and will lead to an undesired deterioration of signal performance. Accordingly, additional contacts through the buried oxide layer and to the substrate are formed to discharge the inherent parasitic capacitors across the buried oxide. Corresponding substrate contacts can be formed either by a sophisticated packaging solution which is very time-consuming and, hence, cost-intensive, or by introducing front side substrate contacts through the buried oxide layer to the substrate.
With reference to
FIG. 1
, a typical prior art device and a typical prior art process for forming the device will be described in order to detail the problems involved with the formation of front side substrate contacts in an SOI device. As the skilled person will easily appreciate, the figures depicting the prior art processing and the prior art device are merely of a schematic nature, and transitions and boundaries illustrated as sharp lines may not be imparted as sharp transitions in a real device. Furthermore, the description of a typical prior art process refers to standard manufacturing procedures without specifying typical parameter values used for those procedures, since the individual processing steps may be slightly varied to meet specific design requirements.
FIG. 1
shows a schematic cross-section of a typical prior art FET device. On a substrate
101
, which may be comprised of a semiconductor material or of any appropriate insulating material, an insulating layer
102
, such as silicon dioxide, is formed. Over the insulating layer
102
, a silicon layer
103
is disposed in which drain and source regions
104
and a channel region
105
are formed. A gate electrode
106
is located over the channel region
105
and spaced apart therefrom by a gate insulating layer
107
. Adjacent to the sidewalls of the gate electrode
106
, sidewall spacers
108
are formed. Over the gate electrode
106
, the drain and source regions
104
and the sidewall spacers
108
, an etch stop layer
109
, which also serves as an anti-reflective coating, is formed. The entire structure is embedded in a dielectric layer
110
having a planarized surface. Moreover, source and drain contacts
111
, a gate electrode contact
112
, and a substrate contact
113
are shown in FIG.
1
. It is to be noted that the gate electrode contact
112
is not on the same plane as the source and drain contacts
111
, since usually the drain electrode is contacted at the ends of the transistor width dimension which, in the case of
FIG. 1
, is the direction that extends in a perpendicular manner to the drawing plane of FIG.
1
.
A typical process for forming the structure shown in
FIG. 1
may comprise the following process flow. After formation of a region of cobalt silicide (not shown) on and in the surface of the drain and source regions
104
and on and in the surface of the gate electrode
106
, a dielectric bi-layer consisting of etch stop layer
109
and dielectric layer
110
is deposited by any appropriate deposition method, such as chemical vapor deposition (CVD). Next, the surface of the dielectric layer
110
is planarized by chemical mechanical polishing (CMP). As already mentioned, the underlying etch stop layer
109
, which may be comprised of a nitride or a silicon oxynitride, has two functions. First, it serves as a bottom anti-reflective coating (BARC) layer for the critical contact hole lithography process. Second, it serves as an etch stop layer so as to allow a common etch step for the formation of openings
112
A,
111
A, respectively, for gate electrode contact
112
and the drain and source contacts
111
, since different etch depths are required for the drain and source contacts, on the one hand, and the gate contact, on the other hand. Before or after the lithography step for forming the openings for the drain, source and gate contacts, a further masking and etch step is carried out to form an opening
113
A for the substrate contact
113
. As can be seen from
FIG. 1
, a stack of different materials has to be anisotropically etched without any undercuts or over-hangs that would disadvantageously affect the filling of the opening with an appropriate metal such as tungsten. Next, all openings
111
A,
112
A,
113
A are filled with a common barrier layer followed by a tungsten deposition so as to form the drain and source contacts
111
, the gate electrode contact
112
, and the substrate contact
113
. Finally, a further CMP step removes the excess barrier material and the excess tungsten material from the wafer surface.
As is clear from the above description, the formation of the front side substrate contact necessitates a difficult etch step for opening a narrow contact hole in a stack of different materials for subsequent refilling by a CVD process. Moreover, according to prior art processing, it may be such that, in forming the substrate contact, a masking step may be performed on a substrate comprising already-opened contacts, leading to further complications and difficulties in conjunction with, for example, application and removal of photoresist and the like.
Accordingly, there exists a need for an improved and cost-efficient method for forming front side substrate contacts for an FET transistor device formed over a buried insulator layer.
SUMMARY OF THE INVENTION
According to the present invention, a method of forming a substrate contact in a field effect transistor comprises providing a substrate with an insulation layer formed thereon, forming a semiconductor layer above the insulation layer, forming a transistor in an active region of the semiconductor layer, forming a first part of the substrate contact, the first part extending through the insulation layer and contacting the substrate, the first part having a first end that extends above a surface of the semiconductor layer, and forming a second part of the substrate contact above the first part of the substrate contact, the second part being electrically coupled to the first end of the first part of the substrate contact.
According to the present invention, the substrate contact of a field effect transistor is formed in two steps so as to eliminate the necessity of etching a contact hole having a large aspect ratio through a layer stack of different materials in a single step.
According to a further embodiment, the method further comprises depositing a dielectric layer stack comprising a stop layer in contact with a gate electrode of the field effect transistor, thinning and planarizing the dielectric layer stack,

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