Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2000-03-09
2002-02-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S106000, C438S108000, C438S113000, C438S455000, C438S458000, C438S460000, C257S678000
Reexamination Certificate
active
06344401
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to integrated circuit chip packages, and more specifically to a method of forming a stacked-die integrated circuit package at a wafer level.
BACKGROUND ART
A chip package is used to protect integrated circuit chips from contamination and damage and is used to provide a durable and substantial electrical lead system for connecting integrated circuit chips, or dice, onto an external printed circuit board or directly into a electronic product. There are numerous advantages to providing a multi-chip integrated circuit (IC) package over single-chip carriers. By placing multiple chips directly on a substrate that provides low-inductance and low-capacitance connections between the chips and the signal/power lines, and that supplies a very dense interconnection network, packaging density and system performance can be improved. The multi-chip package minimizes the chip-to-chip spacing and reduces the inductive and capacitive discontinuities between the chips mounted on the substrate. Additionally, narrower and shorter wires on the ceramic substrate have much less capacitance and inductance than the printed circuit board interconnections. It is often advantageous to stack multiple identical IC chips into the same chip package in order to increase memory without increasing the footprint, or the area occupied on a circuit board, of the integrated circuit package.
In the prior art, it has been common to fabricate a package for each individual pair or group of dice that constitute the multi-chip package. Others have realized that it would be advantageous to be able to form the IC package at the wafer level, that is, after each individual die has been formed on the wafer, but before the wafer has been diced into individual chips. This allows for easier mass production of chip packages and for several chip packages, arranged in a matrix format on the wafer, to be manufactured and tested all at one time. This can reduce time and cost in the process of packaging and testing IC chips.
Most of the wafer level packaging schemes of the prior art involve the packaging of a single integrated circuit die. Other packaging schemes which involve multiple dice often attempt to form the semiconductor devices by stacking a plurality of wafers. For example, U.S. Pat. No 5,952,725 to Ball discloses a method for increasing circuit density by stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back to back with the lower wafer, with a layer of adhesive being applied on the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair. U.S. Pat. No. 5,872,025 to Cronin et al. discloses a stacked 3-dimensional device which is prepared by stacking wafers as an alternative to stacking individual devices. The chip regions are formed on several wafers with each chip region being surrounded by an insulator filled trench. The wafers are then stacked with the chip regions in alignment and joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes.
One problem with methods, such as those noted above, in which whole wafers are aligned to each other, adhered together, and then diced into individual die pairs, is that there is no guarantee that all of the individual die will be “good” and function properly. For example, in aligning the wafers, a good die may be aligned with a “bad” die, or a die that doesn't function properly. A combined stacked-die package which includes both a good die and a bad die would ultimately result in a bad stacked-die package and would have to be discarded. This results in the waste of many good dice.
It is an object of the present invention to provide a method of forming a stacked-die IC package that allows all of the silicon dice on a wafer to be packaged at one time and produces an integrated circuit package that has the smallest possible footprint for a stacked-die package.
It is a further object of the present invention to provide a method of forming a stacked-die integrated circuit chip package that results in only good dice being assembled in the stacked-die package and minimizes any waste of good dice.
SUMMARY OF THE INVENTION
The above objects have been achieved by a wafer-level packaging method which allows all of the semiconductor dice on a wafer to be packaged at one time, and produces a stacked dual/multiple die integrated circuit package. The package produced is a true chip size package which has the smallest possible footprint for the stacked-die package. In the method, the wafer with the smaller sized dice of two wafers can be processed through a metal redistribution process and then solder balls are attached. The wafer is sawed into individual die-size ball-grid array packages. On the wafer with the larger sized dice, a die attached adhesive material is deposited on the front of each die site location that is intended for the attachment of one of the die-size BGA packages. The back side of the BGA die package is placed onto the adhesive material and is cured. A wirebonding operation connects the signals from the die-size BGA package to the circuits of the bottom die formed on the wafer. A coating material, such as epoxy, is disposed on the wafer to cover the wirebond leads and the assembly is then cured. The finished stacked die, while still in the wafer matrix form, facilitates easy indexing for final test or parallel testing. Then, the stacked-die wafer is singulated into individual stacked-die IC packages. The method of the present invention allows for dice with the same or different functions to be combined into a single IC package.
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“Tru-Si Technologies Gives New Life to Moore's Law”, Tru-Si Technologies, Inc., web page online at http//www.trusi.com.
Park, Sang wook et al. “Thermal and electrical performance for wafer level package” 2000 Electronic components and technology conference 0-7803-5908 p. 301-310.*
Amagai et al. “Development of chip scale packages for center pad devices” 1997 Electronic components and technology conference 0-7803-3857 p. 343-352.
Atmel Corporation
Lee Jr. Granvill D
McGuire, Jr. John P.
Schneck Thomas
Smith Matthew
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