Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
2000-03-28
2001-07-31
McDonald, Rodney G. (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S192130, C204S192300, C204S298060, C204S298080, C204S298110, C204S298140
Reexamination Certificate
active
06267852
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the deposition of conducting materials on silicon substrates in integrated circuit manufacturing processes. More particularly, the present invention is directed to conducting material deposition methods with corresponding cleaning techniques which can be conducted in situ in a deposition chamber in integrated circuit manufacturing processes.
2. The Relevant Technology
The integrated circuit manufacturing industry is rapidly progressing in its attempts to miniaturize integrated circuits. This progress is resulting in the development of new electronics products with highly enhanced capabilities. In order to continue in this progression, however, new processes are needed for producing integrated circuits with greater efficiency, greater flexibility, lower power consumption, and lower cost. As an example, one process which must be improved in order to continue the progress being made comprises the deposition of conducting materials on the surface of in-process integrated circuit wafers. When so doing, there is often a need prior to the deposition to remove a native oxide layer which grows on silicon surfaces as a result of a reaction with oxygen. The native oxide layer is insulative and is undesirable as it increases the resistivity of the interface. Other impurities are often present on the surface and must likewise be removed.
Typical processes for removing native oxide layers comprise, for instance, a hydrofluoric acid chemical bath. The hydrofluoric acid chemical bath is typically conducted in a cleaning chamber. After the hydrofluoric acid chemical bath and subsequent drying, the in-process integrated circuit wafer is transferred from the cleaning chamber to a deposition chamber for deposition of a conducting material.
Other processes for removing the native oxide and other impurities comprise plasma etching in a chamber such as a high density plasma etching chamber. This process typically comprises evacuating the high density plasma etching chamber to a low pressure, applying a voltage bias to the in-process integrated circuit wafer, and introducing an inert gas into the high density plasma etching chamber. The inert gas is ionized through collisions with electrons, and the positive ions are accelerated toward the in-process integrated circuit wafer, impacting and dislodging impurities from the surface thereof in a plasma etch. Once again, after the plasma etch is concluded, the in-process integrated circuit wafer is transferred to the deposition chamber.
The deposition of conducting materials, such as the electrically conducting materials of titanium and aluminum, is typically conducted with the use of a type of physical vapor deposition (PVD) known as sputter deposition. In sputter deposition, the in-process integrated circuit wafer is located at the bottom of a PVD deposition chamber and a target formed of the conducting material to be deposited is placed at the top of the PVD deposition chamber. A negative voltage bias is applied to the target, the PVD deposition chamber is evacuated to a low pressure, and an inert gas such as argon is introduced into the PVD deposition chamber. Electrons are separated from the argon atoms due to collisions, and the argon atoms become positively ionized. The argon ions are accelerated toward the target by the voltage bias, impacting and dislodging atoms of the conducting material. The dislodged atoms of the target are expelled with an energy that carries them to the surface of the in-process integrated circuit wafer, where they are deposited.
A collimator is used in order to direct the atoms expelled from the target straight down to the in-process integrated circuit wafer surface so as to maintain high step coverage of geometrical features formed on the surface of the in-process integrated circuit wafer. The collimator comprises an array of tubes located between the target and the in-process integrated circuit wafer. Only atoms that are expelled from the target with a substantially normal angle of incidence to the target pass through the center of the tubes of the collimator and continue on to the in-process integrated circuit wafer. The atoms expelled with an angular trajectory are blocked by the walls of the collimator. This assures that a uniform step coverage of the conducting material over the geometrical features on the surface of the in-process integrated circuit wafer is maintained
A major drawback of prior art deposition processes is that removing the native oxide layer prior to deposition requires an additional chamber. Consequently, more equipment and clean room space are required, at a greater expense. Transferring the in-process integrated circuit wafers between multiple chambers also takes more time, lowering the throughput of the integrated circuit manufacturing process.
A further drawback of current deposition processes is the occurrence of cusping. An example of cusping is illustrated in FIG.
1
. Therein can be seen a silicon substrate
10
of an in-process integrated circuit wafer. A surface
12
on the silicon substrate is shown patterned with a contact opening
14
. A film
16
has been deposited over surface
12
by a process such as the PVD sputter deposition process discussed above. A large buildup of the sputtered conducting material at the surface of contact opening
14
during the sputter deposition of film
16
has caused the occurrence of cusps
18
. Cusps
18
eventually close over the surface of contact opening
14
, resulting in a keyhole
20
in the center of contact opening
14
. Keyhole
20
increases the contact resistance of the contact being formed, which results in slower device performance, which can in turn result in a failure condition of the integrated circuit. Also, keyhole
20
can open up during later processing steps and allow caustic materials inside, which will erode film
16
, also resulting in a failure condition.
Consequently, a need exists in the art for a deposition process whereby the time, space, and expense of the separate chamber necessary for the precleaning step can b eliminated. Such a process would be exceptionally advantageous if it were compatible with conventional PVD sputtering processes, and especially if compatible with collimated PVD sputtering processes. It would also be highly advantageous if the deposition process and preclean could be conducted in a manner whereby the deposition rate and qualities of the conducting material being deposited, and the morphology of the resulting film could be controlled, and whereby the incidence of cusping and keyhole formation could be avoided.
SUMMARY AND OBJECTS OF THE INVENTION
The present invention seeks to resolve the above and other problems which have been experienced in the art. More particularly, the present invention constitutes an advancement in the art by providing a method for cleaning a silicon substrate of impurities prior to the deposition of a conducting material, which achieves each of the objectives listed below.
It is an object of the present invention to provide a method for cleaning a silicon substrate of impurities prior to the deposition of a conducting material, wherein the cleaning step and the subsequent deposition step can both be conducted in the same chamber, thus eliminating the need for additional equipment and space, and eliminating the step old transferring the in-process integrated circuit wafer between chambers, thereby increasing the throughput of the integrated circuit manufacturing process.
It is also an object of the present invention to provide such a method with which a conventional PVD sputter deposition with a collimator can be utilized for the deposition step.
It is additionally an object of the present invention to provide such a method with which a voltage bias can be applied to both an in-process integrated circuit wafer and a target, and wherein the relative voltage bias levels of the in-process integrated circuit wafer and the target can be adjusted, such that the deposition rate and morphology
Givens John H.
Leiphart Shane B.
McDonald Rodney G.
Micro)n Technology, Inc.
Workman & Nydegger & Seeley
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