Method of forming a spin-on-glass insulation layer

Details Method of forming a spin-on-glass insulation layer Method of forming a spin-on-glass insulation layer

2001-10-15

2003-10-21

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S760000, C438S761000, C438S593000, C438S622000, C438S623000, C438S624000, C438S626000

Reexamination Certificate

active

06635586

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-75179, filed on Dec. 11, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method of forming an insulation layer, and more particularly to a method of forming an insulation layer of a semiconductor device using a spin-on-glass (SOG) layer.
BACKGROUND OF THE INVENTION
As the elements incorporated into a semiconductor device are increasingly integrated, the sizes of the elements is gradually decreasing, and the semiconductor devices are becoming increasingly multi-layered. Thus, in highly integrated semiconductor devices, problems such as increase in the aspect ratio of contact or via holes which penetrate a given region between the interconnect lines or the circuit elements and enlargement of the step coverage are more intensified. That is, as the aspect ratio of the contact holes is increased, it becomes more difficult to form deep and narrow holes in certain layers of the device and to fill the narrow holes with conductive material to interconnect the multiple layers. Also, undesirable step coverage at a lower part of the device results in a problem when an upper part of the device is patterned to form the interconnects (wires) or elements by means of photolithography. To reduce these problems, a technique using an interlayer insulation layer such as a method of filling gaps between the elements such as gate lines with the interlayer insulation layer and planarizing the upper part of the interlayer insulation layer has been developed and used.
As an example of the technique using an interlayer insulation layer, there has been proposed a method of forming a boro-phospho silicate glass (BPSG) layer and then performing a heat treatment process at a high temperature of about 830° C. However, since width between gate lines is designed below a critical dimension (CD) of 0.2 &mgr;m with the semiconductor device highly integrated, the heat treatment at the high temperature for forming the interlayer insulation layer may result in a problem damaging the elements, for example reduced transistors in the semiconductor device.
To solve the problem due to the heat treatment at the high temperature, there has been another method of using an O
3
tetra ethyl ortho silicate undoped silicate glass (O
3
TEOS USG), or high density plasma enhanced chemical vapor deposition (HDP CVD) oxide layer. However, these layers also present a problem of generating voids or seams when the width between gate lines is designed below a CD of 0.2 &mgr;m, for example about 0.18 &mgr;m.
To solve the problems described above, there has been used another method of using a spin-on glass (SOG) layer as an interlayer insulation layer. SOG materials are advantageous to fill the gaps between the gate lines and to reduce the step coverage since it is first in a state of liquid or sol.
As one of the SOG materials, hydro silsesquioxane (HSQ) material is used. After the HSQ material is applied to a substrate, a soft bake process is carried out at a low temperature of 100 to 300° C. to remove solvent ingredients. Then, a hard bake process is carried out at a temperature of about 400° C. for several, e.g., ten, minutes to harden the formed HSQ layer.
However, even though the HSQ layer is annealed under an oxidative atmosphere through the hard bake process, a curing of forming silicon dioxide-crystallized structures is not accomplished well. Particularly, in case of using the SOG layer to fill deep and narrow gaps of the pattern, it is difficult to make oxygen and elements combined thereto diffuse. Also, since the curing is carried out at relatively low temperature and begins from the surface of the SOG layer to interfere with the diffusion of oxygen, the HSQ layer is not cured very well.
When the curing of the HSQ layer is not accomplished well, impurity ingredients such as hydrogen and the like may not be removed completely and remain in the HSQ layer. The impurity ingredients may result in a problem such as forming a porous crystallized structure in the HSQ layer. When the following etching and cleaning process is carried out to a portion of the SOG layer having the porous crystallized structure, an etch rate at the portion of the SOG layer comes to be faster than that at other portions without the porous crystallized structure therein.
For example, in case the interlayer insulation layer is formed of the HSQ layer after forming a metal oxide silicon (MOS) transistor structure on a substrate, the porous crystallized structure is apt to be formed in a lower part of the interlayer insulation layer between the gate lines. Therefore, when the pads for bit line contacts or storage node contacts are formed by means of a self-aligned method, the lower part of the SOG layer having the porous crystallized structure is exposed. The exposed lower part of the SOG layer is easily etched by means of a very small amount of etchant contained in a detergent such as a mixture of NH
4
OH, H
2
O
2
and de-ionized water called SCI, or buffered oxide etcher (BOE). As a result, pipe line shaped bridges can be formed between the adjacent pads through the exposed lower part of the SOG layer. These bridges may cause a short circuit between wires, resulting in abnormal operation of the semiconductor device.
Also, in the portion of the SOG layer having the porous crystallized structure, a difference in the stress or tension may be generated according to the thermal expansion and the like as compared with other portions without the porous crystallized structure, resulting in deterioration of reliability of the elements generation of devices of inferior quality.
Among the SOG materials, the silazane series is material indicated as a structural formula —(SiR
1
R
2
NR
3
)n— having average atomic weight of 1000 to 2000. The silazane series usually uses perhydro-polysilazane wherein all of R
1
, R
2
, and R
3
is hydrogen, or organic polysilazane wherein R
1
, R
2
, and R
3
are an alkyl radical of 1-8 carbon atoms, an aryl radical, and an alkoxyl radical, respectively. The perhydro-polysilazane or organic polysilazane which is usually called polysilazane is used as a solution melted as much as a given % by weight in a solvent such as dibuthyl ether, toluene, or xylene. The polysilazane can carry out the heat treatment at higher temperature as compared with silicate, or siloxane series, so that more complete curing can be accomplished. Also, the polysilazane has a high resistance to wet etching, so that it is easy to apply to the real process compared with the HSQ layer. Also, when a polysilazane layer is formed to be relatively thick, a plane state of the whole surface of the substrate can be improved enough to carry out subsequent processes such as a chemical-mechanical polishing (CMP) without forming a capping oxide layer on an upper part of the polysilazane layer.
The polysilazane layer is generally formed by performing a bake process for removing solvent ingredients, and an annealing process for curing formed polysilazane layer at a high temperature of more than 600° C., for example 700° C., after the polysilazane is applied to a substrate. An example of a method of baking and annealing the polysilazane layer is disclosed in Japanese Patent Applicant No. 97-044,132 filed by Nippon Denki Co., Ltd.
FIG. 1
is a flow chart showing the process steps of a conventional method of forming a SOG insulation layer of a semiconductor device. The method comprises forming a pattern on a surface of a substrate (
10
), applying a SOG layer on the surface of the substrate (
20
), performing a pre-bake process to the substrate (
30
), performing a high temperature annealing process to the substrate (
40
), and performing the following or subsequent processes (
50
).
However, in the method, silane (SiH
4
) gases which generally begin to discharge from the SOG layer in the vicinity of a temperature of about 400° C. are generated in a large quantity during the high temperature annealing process and are eas

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