Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-08-23
2001-12-04
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S664000, C438S651000, C438S655000, C438S656000, C438S683000
Reexamination Certificate
active
06326289
ABSTRACT:
FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of forming a silicide region.
BACKGROUND OF THE INVENTION
Titanium silicide has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi
2
has certain advantages relative to other suicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi
2
exists as either an orthorhombic base centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phase), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase). When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required. This second step may be disadvantageous because it can have detrimental effects on the silicide and other integrated circuit elements. However, it may be necessary.
A typical set of processing conditions for forming titanium silicide include: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature about 700° C., (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700° C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept about 700° C. or below in order to minimize over-spacer bridging. The second transformation anneal is performed after any un-reacted titanium and any titanium nitride layers have been selectively removed and is generally performed at temperatures of 50°-200° C. above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance.
It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary to both overcome the nucleation barrier associated with forming the new surface and growing the crystalline structure of the newly-forming C54 phase. In VLSI applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed. In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent.
A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration. As line-widths and silicide film thickness decrease, the thermal energy required to affect the C49-to-C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve.
A method to facilitate the transformation from the C49 phase to the C54 phase involves causing at least a portion of the polycrystalline silicon structure to become amorphous. This can be done by subjecting the polycrystalline silicon structure to preamorphization implant (PAI) prior to the deposition of titanium. As is described in a prior patent application assigned to Texas Instruments, TI-25319, this PAI can be accomplished by implanting either Ge or As into the polycrystalline structure so as to make it amorphous for at least 10 to 30 nm into the structure.
A problem with this method is that introduction of the PAI into the source/drain regions of the transistor can damage the transistor. Specifically, the leakage current is degraded.
SUMMARY OF THE INVENTION
Basically, the instant invention involves a method of performing a PAI which eliminates or reduces the amount of PAI which penetrates into the source/drain regions of the transistor.
An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming the gate structure over the substrate; forming a source/drain regions and a channel region in the semiconductor substrate, the channel region situated between the source/drain regions and under the gate structure; forming a photoresist layer over the source/drain regions; amorphizing a portion of the gate structure by introducing an amorphizing substance into the gate structure; removing the photoresist layer after the step of amorphizing a portion of the gate structure; forming a metal layer on the conductive structure, the metal layer interacts with the gate structure in the amorphized portion of the gate structure and the source/drain regions so as to form a lower resistivity silicide on the gate structure and the source/drain regions; and wherein the photoresist layer blocks the amorphizing substance from the source/drain regions and allows the amorphizing substance to enter the gate structure. Preferably, the gate structure is comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, and any combination thereof, and the metal layer is comprised of a material selected from the group consisting of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof. The amorphizing substance is, preferably, comprised of a substance selected from the group consisting of: As, Ge, or any combination thereof. The photoresist layer may be patterned prior to the step of amorphizing a portion of the gate structure so as to expose the top of the gate structure.
In an alternative embodiment, the method further includes the step of performing a low temperature anneal step after the step of forming a metal layer on the gate structure. Preferably, the low temperature anneal step is performed at a temperature in excess of 600 C. More specifically, the low temperature anneal step is, preferably, performed around 700 to 800 C.
REFERENCES:
patent: 4908331 (1990-03-01), Raaijmakers
patent: 5223445 (1993-06-01), Fuse
patent: 5739064 (1998-04-01), Hu et al.
patent: 5780362 (1998-07-01), Wang et al.
patent: 5893751 (1999-04-01), Jenq et al.
patent: 5895245 (2000-04-01), Harvey et al.
patent: 5904564 (1999-05-01), Park
patent: 5940699 (1999-08-01), Sumi et al.
patent: 6087234 (2000-07-01), Wu
patent: 6107096 (2000-08-01), Mikagi
Wolf and Tauber, “Silicon Processing for the VLSI Era vol. 1: Process Technology”, Lattice Press, 1986, pp. 321-324.*
Fuji et al. “Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputtering” VLSI Technology 1995, pp. 57-58.
Kittl Jorge A.
Rodder Mark S.
Brady III W. James
Fourson George
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Toledo Fernando
LandOfFree
Method of forming a silicide layer using a pre-amorphization... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a silicide layer using a pre-amorphization..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a silicide layer using a pre-amorphization... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2591086