Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-06-04
2004-04-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06727159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of a semiconductor device, more particularly to a method of forming a shallow trench isolation capable of preventing corner erosion of the shallow trench isolation so that the semiconductor device performance can be improved.
2. Description of the Related Art
As semiconductor device dimensions continue to shrink, local oxidation of silicon (LOCOS) isolation structure that has served the technology well into the submicron regime runs up against several foundational limitations. The extension of the “bird beak” taper into the active transistor areas becomes unavoidable as the maximum distance between active regions decreases. In addition, the lack of planarity creates problems, particularly as the sophistication of the interconnection scheme increases.
Shallow trench isolation (STI) formed by high density plasma chemical vapor deposition (HDPCVD) has been used to replace conventional local oxidation of silicon (LOCOS) in order to form improved field isolation structures.
One important advantage of HDPCVD is to effectively fill a dielectric material such as oxide so that the surface is planarized and void-free. However, there may be mechanisms of etching, sputtering, and deposition associated with the plasma technology. Therefore, a HDPCVD process for a oxide material does not only include deposition of oxide layer on the semiconductor substrate surface, but also etching of the semiconductor substrate and sputtering into the recess portion of the semiconductor substrate.
In order to protect the semiconductor substrate form damage by bombardment etching, a method of forming shallow trench isolation described in U.S. Pat. No. 6,146,974 is provided.
As shown in
FIG. 1
, a semiconductor substrate
10
made of single-crystalline silicon is provided. Next, a hard mask HM consisting of pad nitride
14
and pad oxide
12
is formed over the semiconductor substrate
10
. The semiconductor substrate
100
is anisotropically etched to form a shallow trench
16
when the hard mask HM is used as the etching mask. Then, a thermal oxide film
18
is grown on the shallow trench
16
by thermal oxidation. A nitride liner
20
is deposited on the thermal oxide film
18
by chemical vapor deposition.
A silicon oxide
22
is conformally deposited on the nitride liner
20
by high density plasma chemical vapor deposition (HDPCVD) without a bias voltage applied to the semiconductor substrate
10
. In this step, a mixture gas of silane and oxygen having a flow rate of about 1:2 is introduced into the deposition chamber. The conformal silicon oxide
22
has an etching rate higher than 690 angstroms/min using a hydrofluoric acid solution. A silicon oxide
24
is then deposited to fill the shallow trench
16
by high density plasma chemical vapor deposition (HDPCVD) while a bias voltage is applied to the semiconductor substrate
10
. In this step, a mixture gas of silane and oxygen having a flow rate of about 1:2 is introduced into the deposition chamber. The silicon oxide
24
has an etching rate of about 300 angstroms/min using a hydrofluoric acid solution.
The silicon oxide
22
,
24
and nitride liner
20
are planarized by chemical mechanical polishing while the hard mask HM is used as the polishing stop layer. Next, in order to remove native oxide on the pad nitride
14
, the so-called deglaze step is conducted. That is to say, residual oxide (not shown) on the pad nitride
14
is removed by a hydrofluoric acid solution. The conformal silicon oxide
22
is lower than the silicon oxide
24
as shown as
FIG. 1
after the deglaze step because the conformal silicon oxide
22
has a higher etching rate.
Next, as shown in
FIG. 2
, the pad nitride
14
of the hard mask HM is removed to expose the pad oxide
12
by a phosphorus acid solution. In this step, the nitride liner
20
formed on the shallow trench
16
is attacked so as to create a small channel
26
and leave a nitride liner
20
a.
Afterward, as shown in
FIG. 3
, the pad oxide
12
is removed by a hydrofluoric acid etchant. In this step, the thermal oxide film
18
is attacked by the hydrofluoric acid etchant through the small channel
26
so as to create a recess
28
and leave a thermal oxide film
18
a
. Accordingly, the recess
28
can result in poor performance of the semiconductor device such as transistor formed in the subsequent step.
Therefore, a need exists in the industry for a shallow trench isolation process which eliminates corner erosion of shallow trench isolation thereby improving the semiconductor device performance.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method of forming a shallow trench isolation in a semiconductor substrate. According to the method, corner erosion of shallow trench isolation can be eliminated thus improving the performance of the semiconductor device.
Accordingly, the above objects are attained by providing a method of forming a shallow trench isolation in a semiconductor substrate. First, a hard mask consisting of a pad nitride and a pad oxide is formed on the semiconductor substrate. The semiconductor substrate is anisotrpically etched to form a shallow trench while the hard mask is used as the etching mask. A thermal oxide film is then grown on the trench. Then, a nitride liner is formed on the thermal oxide film. Next, a silicon rich oxide layer is conformally deposited on the nitride liner by high density plasma chemical vapor deposition without a bias voltage applied to the semiconductor substrate. Then, a silicon oxide is deposited to fill the trench by high density plasma chemical vapor deposition while a bias voltage is applied to the semiconductor substrate.
Furthermore, the deposition gases for the silicon rich oxide can include a mixture gas of silane and oxygen having a flow ratio of about 1:1.
Furthermore, the deposition gases for the silicon oxide can include a mixture gas of silane and oxygen having a flow ratio of about 1:1 to 1:2.
Furthermore, the silicon rich oxide layer has a hydrofluoric acid selectivity of about 1 or less than 1 relative to the silicon oxide layer.
Furthermore, this method can further comprise the steps of:
planarizing the silicon rich oxide layer and the silicon oxide layer by chemical mechanical polishing while the hard mask is used as the polishing stop layer; and
removing residual oxide above the hard mask by hydrofluoric acid.
Furthermore, the nitride liner is preferably a silicon nitride film formed by chemical vapor deposition.
REFERENCES:
patent: 6146974 (2000-11-01), Liu et al.
patent: 6235606 (2001-05-01), Huang et al.
patent: 6326282 (2001-12-01), Park et al.
patent: 6576530 (2003-06-01), Chen et al.
Chen Yi-Nan
Liu Hsien-Wen
Tzou Kaan-Lu
Ladas & Parry
Nanya Technology Corporation
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