Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-05-03
2001-10-16
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S296000, C438S424000, C438S435000, C438S437000, 43, 43, C430S314000
Reexamination Certificate
active
06303413
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor processing, and in particular, to a method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates.
BACKGROUND OF THE INVENTION
Electrical isolation between active devices is a requirement for integrated circuits. Electrical isolating structures are formed between active devices to reduce unwanted diffusion of dopants between adjacent devices, to prevent and/or reduce capacitance coupling between adjacent devices, and to prevent latch up (i.e. an unwanted forward biasing of a device from interactions with one or more adjacent devices), to name a few.
Although isolating structures improves the performance and reliability of devices and/or integrated circuits, they typically require a substantial footprint to implement. Since there is a trend to reduce the size of devices and integrated circuits, there is a need to make the size of isolating structures as minimal as possible. One existing isolating structure is an oxide formed by local oxidation of silicon (LOCOS). An undesirable characteristic of LOCOS is that it typically requires a relatively large footprint to properly implement it.
An additional problem with existing isolating structures is that they typically produce a non-planarized top surface in the process of forming these structures. A non-planarized top surface is not desired because subsequent processing on a non-planarized top surface is more difficult than on a planarized surface. Otherwise, an undesirable planarization step is required before subsequent processing is performed. The isolating oxide formed by LOCOS typically results in a non-planarized top surface.
Yet, another problem with existing isolating structures is that they typically have adverse effects due to high temperature processes required to form them. As a result, unwanted diffusion of dopants may occur from the high temperature processes. Additionally, unwanted stresses may form between the isolating structures and other adjacent materials. An example of the effect of a known source of stress in existing isolating structure is the stress caused by the formation of the “bird's beak” at the interface of the LOCOS and adjacent nitride layers.
Thus, there is a need for a method of forming an electrical isolating structure that requires a relatively smaller footprint to implement, that results in a more planarized top surface, that is less susceptible to outgassing and unwanted diffusion, and that produces less stress against adjacent materials. In particular, an improved method of forming a shallow and deep trench isolation is provided herein that reduces or eliminates the problems associated with existing electrical isolating structures for devices and/or integrated circuits.
SUMMARY OF THE INVENTION
One aspect of the invention includes a method of forming a shallow-deep trench isolation (SDTI) suitable for silicon on insulator (SOI) wafers that includes the steps of forming deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped polysilicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then shallow trenches are formed. The shallow trenches are formed using a low selectivity etch to uniformly etch a deep trench liner oxide, the active nitride and underlying oxide layers, SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etch. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.
More specifically, a method of forming a shallow and deep trench isolation in a silicon on insulator (SOI) wafer is provided as an aspect of the invention. The SOI wafer comprises a silicon on insulator (SOI) layer disposed on a buried oxide layer which is, in turn, disposed on a handle wafer. The method comprises the steps of forming a layer of a hard mask oxide on the top surface of the SOI layer, and then forming at least one window through the mask oxide layer to expose the underlying SOI layer. Then, a deep trench is formed through the SOI layer down to the buried oxide layer by removing a portion of the SOI layer underlying the window of the mask oxide layer. Then, the hard mask oxide is removed using an etching process that is characterized by a relatively high etching ratio of the hard mask oxide to the buried oxide layer. The removal of the hard mask oxide thereby minimizes the etching of the buried oxide layer.
Following the removal of the hard mask oxide, a liner oxide material is formed on the sidewall of the deep trench and the wafer surface. Then, the deep trench is filled with an electrical isolating material such as a doped or undoped glass (dielectric) or an undoped polysilicon. The electrical isolating material is then etched back to remove the material above the SOI layer and substantially planarize the top surface of the SOI wafer at this point of the process. Following the etch back procedure, an active area pad oxide and nitride layers are deposited over the SOI layer and then a shallow trench is formed over the deep trench by removing portions of the active area layer, the SOI layer, the deep trench liner oxide, and the electrical isolating material. Because the interfaces of the SOI layer, the deep trench liner oxide, and the electrical isolating material are at non-perpendicular angles with respect to the direction of the etching during the shallow trench formation, a low selectivity etching process is used so that the etching rates of these materials are substantially the same. This forms a substantially planarized shallow trench floor. Once the shallow trench is formed, it is filled with an electrical isolating material.
This method of the invention has several advantages over the prior art methods of forming isolating structures for active devices. First, the method of the invention forms the shallow-deep trench isolation (SDTI) with a substantially planarized top surface. This makes subsequent processes easier to perform because of the planarized top surface, and also helps in the planarization of the final product. Second, since the method does not use a local oxidation of silicon (LOCOS) which typically requires a relatively large footprint, much smaller dimensions for the devices and/or integrated circuits can be formed using the method of forming a shallow-deep trench isolation (SDTI) in accordance with the invention. Third, since the deep trench fill material is buried and encapsulated by the overlying shallow trench fill, outgassing and unwanted diffusion of the deep trench fill material is reduced. This allows the use of such low stress materials as a heavily doped BPSG glass.
REFERENCES:
patent: 5516625 (1996-05-01), McNamara et al.
patent: 5589415 (1996-12-01), Blanchard
patent: 5719085 (1998-02-01), Moon et al.
Choutov Dmitri A.
Dobson Thomas W.
Kalnitsky Alexander
Liao Ken
Scheer Robert F.
Blakely , Sokoloff, Taylor & Zafman LLP
Luu Pho
Maxim Integrated Products Inc.
Zarabian Amir
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