Method of forming a semiconductor device using selective...

Details Method of forming a semiconductor device using selective... Method of forming a semiconductor device using selective...

2002-01-10

2003-05-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S723000, C438S268000

Reexamination Certificate

active

06562707

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-18506, filed on Apr. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device using selective epitaxial growth (SEG).
2. Description of the Related Art
The Selective Epitaxial Growth (SEG) method enables a single crystalline silicon layer to be grown only on a selected area of the substrate. Therefore, regions where the epitaxial growth will occur must first be defined before actually performing the epitaxial growth.
The epitaxial growth region is defined by selectively exposing a portion of the substrate. For example, an insulating layer such as a silicon oxide is removed through a photolithography and etching process, exposing a silicon substrate. The exposed silicon substrate enables epitaxial growth and is called a seed window.
The SEG method may be used for trench isolation techniques or contact techniques as well. In the trench isolation method using SEG, the oxide layer is first formed on the silicon substrate. In the conventional method, a trench is formed in the silicon substrate through an etching process and filled with oxide layer. The oxide layer is then patterned using an anisotropic etching technique, forming a trench that exposes the substrate. An epitaxial layer is selectively grown on the exposed substrate. As a result, the trench is filled with the selective epitaxial layer. Here, the epitaxial layer acts as an active region and the patterned oxide layer acts as an isolation region. A discrete device such as a MOS transistor is formed at the active region.
One drawback due to the high integration density of semiconductor devices is that the width of the contact hole is reduced. The contact hole should be filled with a conductive layer such as a metal layer or a polysilicon layer. A chemical vapor deposition (CVD) process is widely used to form the conductive layer. In this case, it is difficult to fill the contact hole due to a high aspect ratio. However, even though the contact hole has a high aspect ratio, the contact hole can be completely filled with the epitaxial layer. The epitaxial layer in the contact hole is referred to a contact plug. The selective epitaxial growth in the contact hole is performed after a gate electrode and source/drain regions are formed on the substrate.
Furthermore, if over etching occurs when forming contact holes in source/drain regions with a shallow junction depth, the substrate under the source/drain regions may be exposed or the depth of the source/drain regions reduced. In addition, if the contact plug is formed of a metal such as tungsten or aluminum, a junction spiking phenomenon might occur due to the shallow junction depth. However, if the contact plug is formed after the source/drain regions are elevated by a silicon epitaxial layer, it is possible to prevent junction spiking as well as void formation.
In the mean time, the anisotropic etching step, such as Reactive Ion Etching (RIE), or ion implantation, are usually performed prior to the selective epitaxial growth. Therefore, physical damage caused by etching or ion implantation generates defects directly on the surface of the substrate. The epitaxial growth is largely affected by the surface state of the substrate. That is to say, growing a single crystal layer can be difficult, if the selective epitaxial growth occurs on a defective substrate. On a defective substrate, the selective epitaxial growth rate is greatly reduced or an epitaxial layer with a single crystalline structure may never form.
Moreover, the active region formed on a defective substrate through the selective epitaxial growth process may have crystalline defects. Therefore, any MOS transistor formed on an active region with crystalline defects may exhibit undesirable device characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of forming a semiconductor device using selective epitaxial growth, which can produce a high-integrity single crystalline semiconductor layer.
It is another object of this invention to provide a method of forming a semiconductor device using selective epitaxial growth, which is capable of increasing process margin and epitaxial growth rate.
These and other objects, advantages, and features of the present invention are provided by a method of forming a semiconductor device using selective epitaxial growth. This method improves the quality of the epitaxial layer. According to one aspect of the present invention, the method includes forming a window for selective epitaxial growth on a semiconductor substrate. The window exposes a region of the substrate. The exposed surface of the substrate is cleaned with a hydrofluoric acid solution, thereby removing a first oxide layer (e.g. a native oxide layer) that exists on the exposed substrate. The exposed substrate is oxidized, thereby forming a second oxide layer (e.g. a sacrificial oxide layer) on the cleaned surface exposed by the window. The second oxide layer is removed to expose a region of the substrate within the window. A selective epitaxial growth process is then performed on the exposed region of the substrate.
The first and second oxide layers may be removed using diluted hydrofluoric acid, which is called a buffered oxide etchant (BOE). Also, the second oxide layer may be formed using a standard cleaning
1
(SC
1
) solution. The SC
1
solution is a mixture of ammonium hydroxide, hydrogen peroxide and de-ionized water at a predetermined volume ratio.


REFERENCES:
patent: 6020239 (2000-02-01), Gambino et al.
patent: 6127230 (2000-10-01), Tang et al.
patent: 6165279 (2000-12-01), Tsao et al.
patent: 6204532 (2001-03-01), Gambino et al.
patent: 6372657 (2002-04-01), Hineman et al.
patent: 2001/0014504 (2001-08-01), Moon
Wolf et al, Silicon Processing For The VLSI Era 1986, Lattice Press, vol. 1, p. 520.

Affiliated with

Also associated with

Rating

Method of forming a semiconductor device using selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a semiconductor device using selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a semiconductor device using selective... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3035593