Method of forming a semiconductor device using double...

Details Method of forming a semiconductor device using double... Method of forming a semiconductor device using double...

2001-05-31

2002-04-23

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Optical characteristic sensed

Reexamination Certificate

active

06376262

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device and, more particularly, to a method of forming a semiconductor device using double endpoint detection.
2. Description of the Related Art
A side wall spacer is a region of material that adjoins the gate of a MOS transistor to electrically isolate the gate from adjacent structures. Side wall spacers are also commonly used during the fabrication of MOS transistors to partially define the areas where the heavily-doped source and drain regions are formed.
FIG. 1
shows a cross-section diagram that illustrates a standard MOS transistor
100
. As shown in
FIG. 1
, MOS transistor
100
, which is formed in a p-substrate
110
, includes spaced-apart n-type source and drain regions
112
and
114
which are formed in substrate
110
, and a channel region
116
that is defined between source and drain regions
112
and
114
.
MOS transistor
100
also includes a layer of gate oxide
120
that is formed over channel region
116
, and a gate
122
that is formed on gate oxide layer
120
over channel region
116
. In addition, a side wall spacer
124
is formed to adjoin the side walls of gate
122
(spacer
124
contacts all four side walls of gate
122
). Side wall spacer
124
is conventionally formed by depositing a layer of oxide over substrate
110
and gate
122
, and then anisotropically (vertically) etching the oxide until the oxide is removed from the top surface of gate
122
.
Although side wall spacer
124
is a common solution for devices with larger feature sizes, e.g., 0.5 microns and above, a complex side wall spacer has been suggested for use in devices with smaller feature sizes, e.g., 0.18 microns. Complex side wall spacers utilize an “L”shaped layer of nitride to dictate the implant junction location of the transistor.
FIG. 2
shows a cross-section diagram that illustrates a MOS transistor
200
with a prior-art complex side wall spacer. Transistor
200
is similar to transistor
100
and, as a result, utilizes the same reference numerals to designate the structures that are common to both transistors.
As shown in
FIG. 2
, MOS transistor
200
differs from MOS transistor
100
in that transistor
200
utilizes a complex side wall spacer
210
. Spacer
210
, in turn, includes an L-shaped insulation layer
212
that adjoins gate
122
, an L-shaped nitride layer
214
that is formed on layer
212
, and a pie or wedge-shaped insulation layer
216
that is formed on nitride layer
214
.
One of the advantages that spacer
210
provides over spacer
124
is that spacer
210
provides greater consistency in transistor parametrics. This, in turn, increases the reliability of the transistors and the manufacturing yield. The complex side wall spacer also has the advantage of being formed with low-temperature processing steps.
FIGS. 3A-3D
show cross-sectional diagrams that illustrate a prior-art method
300
of forming transistor
200
. As shown in
FIG. 3A
, method
300
utilizes a wafer
310
that has been partially-processed to have a p-substrate
312
, and a layer of gate oxide
314
that is formed on substrate
312
. In addition, wafer
310
also has a gate
316
that is formed on gate oxide layer
314
.
Method
300
begins by implanting substrate
312
and gate
316
with an n-type dopant to form n-source and drain regions
320
and
322
in substrate
312
, and dope gate
316
. Following this, as shown in
FIG. 3B
, a layer of tetraethylorthosilicate (TEOS)
324
approximately 300Å thick is formed on oxide layer
314
and gate
316
.
Next, a layer of nitride
326
approximately 300Å-500Å thick is formed on TEOS layer
324
. Once nitride layer
326
has been formed, a layer of TEOS
328
approximately 5,000Å thick is formed on nitride layer
326
. The actual thickness of each deposited layer (TEOS layer
324
, nitride layer
326
, and TEOS layer
328
) can vary from wafer to wafer, and from lot to lot by up to 10%. Since TEOS layer
328
is the thickest, this is most pronounced in TEOS layer
328
. This is illustrated in
FIG. 3B
with two different thicknesses of TEOS layer
328
.
Following this, as shown in
FIG. 3C
, TEOS layer
328
is anisotropically etched for a predetermined period of time (the etch time) to remove TEOS layer
328
from nitride layer
326
over gate
316
and the peripheral region of substrate
312
. The etch time for a layer of material is calculated by considering the expected variation in the incoming film thickness and in the etch rate of the reactive ion etch (RIE) chamber.
The etch time must take into account the worst-case film thickness, i.e., a film that is on the thick side of the film thickness specification (film thickness varies from wafer-to-wafer and lot-to-lot). In addition, the etch time must also take into account the worst-case etch rate, i.e., an etch rate that is on the slow side of the etch rate specification (etch rates will vary depending on chamber condition- newly cleaned to end-of-cycle).
Next, as shown in
FIG. 3D
, nitride layer
326
is anisotropically etched for a predetermined period of time (the etch time) to remove nitride layer
326
from TEOS layer
324
over gate
316
and the peripheral region of substrate
312
. The etch time of nitride layer
326
is determined in the same manner as the etch time of TEOS layer
328
. After this, a source and drain implant is performed through TEOS layer
324
. The implant forms n+source and drain regions
330
and
332
in substrate
312
, and again dopes gate
316
.
One problem with method
300
, however, is that since TEOS layer
328
can have a significant variation in thickness, and layers
314
,
324
, and
326
are relatively thin, a timed etch will occasionally be too long and etch through layers
314
,
324
, and
326
into substrate
312
. The trenching of substrate
312
, in turn, often leads to inoperable devices due to variations in the implant depth. Thus, it is essential to the success of the L-shaped spacer to consistently etch the same amount into TEOS layer
324
.
One approach to this over etch problem is to use optical endpoint detection in lieu of timing the etch. The use of optical endpoint detection is well known, and commercial systems that are reliable in manufacturing have been available for a number of years. One example is the TEL EPD 202 manufactured by Tokyo Electron Limited.
In operation, optical endpoint detection systems monitor the optical components of the plasma during an etch. Some of the optical components, in turn, are specific to the material that is etched. Thus, by monitoring a wavelength of light that is specific to the material being etched, the system can detect when one film has been removed from another film.
For example, a strong peak at 387 nm indicates that CN is present in the plasma, usually indicating that nitride is being etched. Thus, by monitoring the intensity of the light at 387 nm during the etch of nitride layer
326
, the etch can be stopped when the intensity of the light at 387 nm decreases to a point that corresponds with the necessary removal of nitride layer
326
.
Thus, where a timed etch would continue even though nitride layer
326
had been completely removed from over gate
316
and the peripheral area, an optical endpoint system stops the etch as soon as the nitride has been removed. As a result, optical endpoint detection systems improve the uniformity of the final thickness of TEOS layer
324
and reduce the likelihood that the substrate or surface silicon will be trenched or roughened during the etch.
Although satisfactory results can be obtained by using an optical endpoint detection system, there is a need for additional methods of forming complex side wall spacers.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a semiconductor device, such as complex side wall spacers and other structures, that utilizes optical endpoint detection to stop the last n etches used to form the spacers or other structures, where n is equal

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