Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
1999-03-02
2002-09-17
McDonald, Rodney G. (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S192150, C204S192120, C204S192300, C204S298060, C438S582000, C438S652000, C438S653000, C438S656000, C438S685000, C438S698000
Reexamination Certificate
active
06451181
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and more particularly to barrier/seed deposition processes for copper interconnects.
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, copper is currently being developed as a replacement material for aluminum in interconnects. Copper interconnects are generally improved over aluminum interconnects because the manufacturing of copper is less expensive. In addition, copper interconnects are less resistive than aluminum interconnects and, therefore, generate less heat. Also, the reduced resistance of copper improves the ability of the IC to operate at higher operational frequencies, whereby performance is improved. In addition, copper also has improved electromigration resistance as compared to aluminum.
However, in spite of these advantages, copper has a number of disadvantages which must be overcome if it is to become a viable alternative. One disadvantage of copper includes its potential as a source of mobile ion contamination. Copper ions readily diffuse through conventional dielectric materials used in fabricating semiconductors. If not properly contained, copper can diffuse into active areas of the device and thereby impact device reliability. In addition, copper is not easily etched. It therefore requires that interconnects be formed as inlaid structures, which are more complicated and which require using chemical mechanical polishing (CMP) processes. Further, copper processing requires using new materials and new processes which, if not properly integrated into the manufacturing process, can present a variety of problems and complications.
For example, barrier layers are typically required when using copper interconnects. The barrier layer is formed around the copper to contain it, thereby preventing it from contaminating adjacent layers and active regions. These barrier layers, which are generally not required for aluminum, are creating new manufacturing and integration issues which must be addressed. The materials and processes used to form these barriers are currently not well understood. Therefore, further improvements in these materials and the processes for forming them have the potential to significantly enhance wafer yield, device reliability, and equipment uptime.
Many of the materials (e.g., refractory metals) used for barriers in copper processing also have an ability to negatively impact device reliability. These reliability issues stem, in part, from the stress of the barrier layer relative to adjacent films. Therefore, barrier stress control also has the potential to improve the overall IC yield and reliability.
Furthermore, processes and chambers currently used to deposit copper in the interconnects are not optimized in terms of thickness and uniformity control. The lack of control is problematic. If uniformity of the deposited copper film varies enough, yield can be adversely affected and/or subsequent processes may be further complicated by requiring that adjustments be made to compensate for the nonuniformly deposited film.
Additionally, the lack of adhesion of copper and copper barrier materials to chamber components can present problems during deposition as well as during wafer transport. These materials are a potential particle source. Optimizing the deposition process to improve adhesion of these materials would be advantageous to improving yield and reducing particulate contamination in processing chambers.
Many copper processes have step coverage problems wherein the via and trench sidewalls are covered to a lesser extent by the copper film than are planer surfaces. In addition, copper voiding problems can also result if the deposited film at the upper portions of the openings is deposited at too high of a rate. This can cause the film to be pinched off, at the top, before completely filling the opening and result in voids being formed within the opening. A process which improves step coverage and minimizes voiding has the potential to enhance yield and reliability for devices having copper interconnects.
Further, back-sputtering of material during pre-metal deposition processes, which is not necessarily a problem with aluminum, is a concern with copper because of the mobile ion concerns cited previously. If aluminum is back-sputtered onto exposed wafer surfaces, chemicals and processes exist to remove it. In addition, this aluminum does not readily diffuse through the various layers. Contrarily, back-sputtered copper is not easily removed, either chemically or otherwise. Unless it is contained with a barrier, it will likely diffuse through adjacent films and impact yield and reliability. Therefore, any interconnect processes which expose underlying copper layers should be engineered to ensure minimal removal of copper from the exposed regions.
Therefore, a need exists in the industry for improved metallization processing whereby copper interconnects can be manufactured in high volumes, with reduced cost, and improved yield and reliability.
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EPO 00104085 Search Report, 2 pgs.
Anthony Brian G.
Denning Dean J.
Garcia Sam S.
Hamilton Gregory Norman
Islam Md. Rabiul
McDonald Rodney G.
Motorola Inc.
Rodriguez Robert A.
Witek Keith E.
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