Method of forming a self aligned trench in a semiconductor...

Details Method of forming a self aligned trench in a semiconductor... Method of forming a self aligned trench in a semiconductor...

2001-09-21

2003-05-20

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S763000, C438S764000, C438S787000

Reexamination Certificate

active

06566219

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices more particularly to a trench memory device with a vertical transistor and method of forming the same.
BACKGROUND OF THE INVENTION
As is known in the art, dynamic random access memories (DRAMs) are used extensively in a wide range of applications. A DRAM typically includes an array of memory cells, each cell comprising a pass transistor, typically a metal oxide semiconductor field effect transistor (MOSFET), coupled in series with a capacitor.
A portion
10
of an array is shown in
FIG. 1
, which illustrates two complementary pairs of bitlines BL and BL′. While this figure only illustrates eight memory cells, it is known to fabricate DRAMs with over one billion cells. Each bitline pair BL and BL′ is coupled to equalization/precharge circuitry and a sense amplifier, collectively labeled
12
. Although not illustrated, many bitline pairs (and respective circuitry
12
) will be provided.
Each memory cell includes a pass transistor
14
coupled in series with a capacitor
16
. As shown in the figure, one source/drain region of transistor
14
is coupled to the bitline BL (or BL′). The other source/drain region is coupled to one of the plates of respective capacitor
16
. The other plate of capacitor
16
is coupled to a common plate reference voltage.
To select a particular memory cell, a select voltage is applied to one of the wordlines WL
0
-WL
3
. As illustrated in
FIG. 1
, the gate of each pass transistor
14
is coupled to one of the wordlines WL
0
-WL
3
. As shown, each wordline will extend across other bitlines and couple to the gates of pass transistors of memory cells coupled to those bitlines.
The bitline pair BL
0
and BL
0
′ (or BL
1
and BL
1
′) is selected by applying a select voltage to the select transistors
18
and
18
′. When the select transistors
18
and
18
′ are selected, the differential voltage signal across the bitline pair will be transferred to input/output lines I/O and I/O′. In this manner, the state stored in the one memory cell that is coupled to the selected wordline and selected bitline will be transferred to the input/output lines.
Semiconductor memory density is typically limited by a minimum lithographic feature size that is imposed by lithographic processes used during fabrication. There is a continuing need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs.
One way of increasing the data storage capacity of semiconductor memories is to reduce the amount of integrated circuit horizontal planar area consumed by each memory cell. For horizontally oriented devices, this may be done by decreasing the size of the access FET or the storage capacitor, or both. This approach has limits, however, due to minimum producible structure size in a given fabrication technology, and the problems associated with devices with small dimensions, such as hot carriers, punch through, and excess leakage.
Another way of providing planar area reduction is the use of a three-dimensional arrangement of the access FET and the storage capacitor. One such arrangement is a planar FET next to a deep trench capacitor. The trench capacitor has plates which are located vertically along the walls of the trench instead of being parallel to the surface of the integrated circuit substrate. This permits a large capacitance per planar unit area of substrate, while at the same time allowing the device to be of a manageable size for purposes of operation.
To still further reduce the amount of planar area required for each cell, it has been proposed to use a vertical trench transistor in conjunction with a vertical trench capacitor in a memory cell. In a typical design, the vertical capacitor is generally fabricated in a trench, with one conductive plate being formed in the substrate, the dielectric being formed on the trench sidewalls, and the other conductive plate being formed in the interior of the trench. A vertical trench transistor is generally fabricated adjacent to an upper portion of the trench, with the source and drain being fabricated in the substrate, and the vertically-oriented gate being fabricated in the trench.
SUMMARY OF THE INVENTION
In one aspect, the present invention is related to the formation of a trench in a semiconductor region. In one aspect, a first layer of a first material (e.g., polysilicon) is formed over a semiconductor region (e.g., a silicon substrate). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench can be etched in the semiconductor region. The trench would be substantially aligned to the second material.
This process can be advantageously used in the formation of a dynamic random access memory (DRAM) device. In such a DRAM process, the deep trench could be self-aligned with the active area. In other process flows, a significant problem is often found with the formation of the deep trench. If the deep trench is formed before the active area, an overlay problem may occur. This misalignment can influence device performance. The present invention overcomes this problem by forming the active area self aligned to the deep trench. As a result, no overlay is required.
Using this process can lead to smaller device cells. Efforts to realize cell sizes below 8F
2
(where F is the minimum feature size) suffer from either low capacitance area or/and increased sensitivity to overlay. One reason is the strong dependence of the deep trench RIE (reactive ion etch) depth to the deep trench opening. The layout of the preferred embodiment of the present invention provides a complete self-aligned active area to deep trench process flow and a deep trench opening of 1F×2F. This deep trench size should provide sufficient capacitance to obtain storage capacitance of at least about 35fF for F=135 nm and beyond. All of this is achieved with a memory cell that can be scaled to sub-6F
2
cell size.
In addition, the preferred DRAM device uses a single-sided junction, that is there is a single bit for each bitline contact. The concept of a single sided junction leads to a reduced leakage and allows an increased scalability down to 100 nm.
Furthermore, the self-aligned active area to deep trench process provides a well controlled width of the active area. This control leads to a better control of the threshold voltage (Vt) within field, wafer and lot. Since the layout is lithographic friendly, it is possible to build devices with a minimum feature size of 120 nm with commercially available tools.


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“Self-Aligned Polycide Bit Line Structure,” IBM Technical Disclosure Bulletin, vol. 30 No. 12, May 1998, pp. 109-110.

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