Method of forming a self-aligned silicide on a semiconductor...

Details Method of forming a self-aligned silicide on a semiconductor... Method of forming a self-aligned silicide on a semiconductor...

2000-06-01

2001-06-26

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S299000, C438S308000, C438S655000, C438S686000

Reexamination Certificate

active

06251779

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a self-aligned silicide, abbreviated as salicide, on a semiconductor wafer, and more particularly, to a method of forming a cobalt-containing salicide on a semiconductor wafer.
2. Description of the Prior Art
Self-aligned silicide, (salicide) is applied widely in the formation of a MOS transistor to reduce the sheet resistance, and hence provide the devices of the MOS transistor and the metal good ohmic contacts. In the prior art method of forming the salicide, the rapid thermal process is applied in the thermal silicidation process. However, rapid thermal technology is still developing at present time, limiting the yield of the salicide process. Therefor, how to improve the rapid thermal process to enhance the yield of the salicide process becomes a very important issue in the formation of the MOS transistor.
Please refer to FIG.
1
and FIG.
2
.
FIG. 1
is a schematic diagram of a cobalt-containing salicide
20
on a MOS transistor
10
according to the prior art.
FIG. 2
illustrates the relation between time and temperature for the first rapid thermal process in the prior art method of forming a salicide. The MOS transistor
10
is positioned on the surface of a semiconductor wafer
22
and isolated from other devices by shallow trenches
24
formed by using the shallow trench isolation method. The MOS transistor
10
comprises a poly-silicon gate
12
, a gate insulation layer
13
, two spacers
14
, a source
16
and a drain
18
. Cobalt-containing salicides
20
are formed on the surface of the poly-silicon gate
12
, the source
16
and the drain
18
.
In the prior art method of forming the cobalt-containing salicide
20
, a cobalt-containing metallic layer
26
is deposited on the MOS transistor
10
, and then a first rapid thermal process is performed to rapidly heat the semiconductor wafer
22
up to 400~680° C. The high temperature is maintained for 10~40 seconds and then cooled down. This first rapid thermal process allows a portion of metals in the cobalt-containing metallic layer
26
react with poly-silicon of the gate
12
and silicon of the source
16
and the drain
18
, resulting in the formation of CoSi or Co
2
Si.
As shown in
FIG. 2
, during the first rapid thermal process, the temperature is rapidly increased up to T
1
in a period for t
1
seconds (about 10 seconds), wherein T
1
is between 400~680° C. Then the high temperature is maintained at T
1
during the period of (t
2
-t
1
) (for about 10~40 seconds) and cooled down at about the 20
th
~50
th
second of the first rapid thermal process.
After performing the first rapid thermal process, a wet etching process is performed to remove the unreacted or remaining cobalt on the MOS transistor
10
. Then a second rapid thermal process is performed to convert CoSi or Co
2
Si into CoSi
2
with low resistance so as to form the cobalt-containing salicide
20
in the interface between silicon and poly-silicon. Because of the low resistance of CoSi
2
the resistance between cobalt and silicon, or cobalt and poly-silicon can be reduced.
In the prior art method of forming the salicide, the temperature of the first rapid thermal process allows cobalt and silicon to react and form a complex-phase structure which comprises not only CoSi or Co
2
Si but also CoSi
2
co-exiting with CoSi. As a result, CoSi or Co
2
Si cannot be completely converted into CoSi
2
with low resistance in the second rapid thermal process, increasing the resistance of the cobalt-containing salicide. Besides, using a transmission electron microscope to observe the cobalt-containing salicide formed by the prior art method, there was a defect found in it. Therefore, the yield of the salicide process may be reduced.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a self-aligned silicide containing cobalt on a semiconductor wafer to solve the above mentioned problems.
In a preferred embodiment, the present invention provides a method of forming a self-aligned silicide (salicide) on a semiconductor wafer, the surface of the semiconductor comprising at least one silicon device, the method comprising:
forming a cobalt-containing metallic layer on the semiconductor wafer which covers on the surface of the silicon device;
performing a first thermal treatment process to rapidly heat the semiconductor wafer up to 300~500° C. for 10~50 seconds and form a first silicide on the surface of the silicon device;
performing a second thermal treatment process to rapidly heat the semiconductor wafer up to 400~680° C. for 20~50 seconds and then cool down the semiconductor wafer afterwards so as to convert the first silicide into a second silicide;
performing an etching process to remove the metallic layer positioned on the surface of the semiconductor wafer; and
performing a third thermal treatment process to rapidly heat the semiconductor wafer up to 700~950° C. for 30~60 seconds and then cool down the semiconductor wafer afterward so as to convert the second silicide into the self-aligned silicide.
It is an advantage of the present invention that the method can reduce the resistance of the salicide and provide the MOS transistor and the metal a good ohmic contact, and hence enhance the yield of the salicide process.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5877085 (1999-03-01), Matsubara
patent: 5940699 (1999-08-01), Sumi et al.
patent: 6096628 (2000-08-01), Greenlaw et al.
patent: 6159856 (2000-12-01), Nagano
patent: 651077 A1 (1995-05-01), None
patent: 800204 A2 (1997-10-01), None
patent: 936664 A2 (1999-08-01), None

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