Method of forming a self-aligned silicide

Details Method of forming a self-aligned silicide Method of forming a self-aligned silicide

1998-06-24

2000-01-18

Chauduri, Olik

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

H01R 1310

Patent

active

060157534

ABSTRACT:
A method of forming a self-aligned salicide is provided. The invention twice performs selective epitaxial growth to form an amorphous silicon layer on gate electrodes and source/drain regions of a substrate after forming the gate electrodes and the source/drain regions. Then, a molybdenum impurity is doped to perform a silicidation process and to convert a metal deposited on the substrate into a salicide layer.

REFERENCES:
patent: 5824586 (1998-10-01), Wollesen et al.
patent: 5902125 (1999-05-01), Wu
Kittl, J. A., Q.Z., Rodder, M., Breedijk, T.. Novel Self-Aligned Ti Silicide Process for Scaled CMOS Technologies with Low Sheet Resisteance at 0.06-.mu.m Gate Lengths. IEEE Electron Device Letters, vol. 19, No. 5, pp. 151-153, May 1998.
Ohmi, Ti., Hashimoto, K., Morita, M., Shibata, T.. In Situ Doped Epitaxial Silicon Film Growth at 250.degree.C by an Ultra Clean Low Energy Bias Sputtering. Electron Devices Meeting, 1989. Technical Digest., International, 1989, pp. 53-56.
Wakabayashi, H.; Yamamoto, T.; Tatsumi, T.; Tokunaga, K.;Tamura, T.; Mogami, T.; Kunio, T.. A High-Performance 0.1 .mu.m CMOS with Elevated Salicide Using Novel Si-SEG Process.Electron Devices Meeting, 1997. Technical Digest., International, 1997, p. 9.

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