Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2005-01-04
2005-01-04
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S174000, C438S571000, C438S704000
Reexamination Certificate
active
06838325
ABSTRACT:
A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch. The second wet chemical etch selectively removes exposed portions of the ohmic contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, the Schottky contact layer and the etch stop layer. The etch stop layer is removed. A metal layer is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky contact layer.
REFERENCES:
patent: 4616400 (1986-10-01), Macksey et al.
patent: 4839310 (1989-06-01), Hollis et al.
patent: 4908325 (1990-03-01), Berenz
patent: 5021857 (1991-06-01), Suehiro
patent: 5140386 (1992-08-01), Huang et al.
patent: 5270228 (1993-12-01), Ishikawa
patent: 5364816 (1994-11-01), Boos et al.
patent: 5504353 (1996-04-01), Kuzuhara
patent: 5556797 (1996-09-01), Chi et al.
patent: 5654214 (1997-08-01), Frijlink et al.
patent: 6060402 (2000-05-01), Hanson
patent: 6180968 (2001-01-01), Kasahara et al.
patent: 6194747 (2001-02-01), Onda
patent: 6242293 (2001-06-01), Danzilio
patent: 6258639 (2001-07-01), Rohdin et al.
patent: 6524899 (2003-02-01), Grundbacher et al.
patent: 6586113 (2003-07-01), Bahl et al.
patent: 6620662 (2003-09-01), Hoke et al.
patent: 6627473 (2003-09-01), Oikawa et al.
patent: 198 27 901 (1999-01-01), None
patent: 0 855 748 (1998-07-01), None
patent: 09 045894 (1997-06-01), None
Copy of International Search Report for PCT/US03/32687 dated Mar. 11, 2004.
K. Alavi, et al., “A Very High Performance, High Yield, and High Throughput Millimeter Wave Power pHEMT Process Technology”, CaAs Mantech Conference, May 21-24, 2001 pp. 105-107.
Ronald Grundbacher, et al., “Utilization of an Electron Beam Resist Process to Examine the Effects of Asymmetric Gate Recess on the Device Characteristics of AlGaAs/InGaAs PHEMT's”, IEEE Transactions on Electron Devices, vol. 44, No. 12, Dec. 1997, pp. 2136-2142.
Tong Elsa K.
Whelan Colin S.
Daly, Crowley & Mofford LLP
Lebentritt Michael
Raytheon Company
LandOfFree
Method of forming a self-aligned, selectively etched, double... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a self-aligned, selectively etched, double..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a self-aligned, selectively etched, double... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3366508