Method of forming a self-aligned contact pad for use in a...

Details Method of forming a self-aligned contact pad for use in a... Method of forming a self-aligned contact pad for use in a...

2002-04-04

2004-03-16

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S633000, C438S637000, C438S675000, C257S520000, C257S621000

Reexamination Certificate

active

06706633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method of forming a self-aligned contact pad for use in a semiconductor device.
2. Description of the Related Art
As methods for forming semiconductor devices become more complex, a bar-type self-aligned contact (SAC) process is used in a method for forming a direct contact (DC) pad and a bit line contact (BC) pad instead of a more conventional hole-type SAC. The method for forming a DC pad and a BC pad additionally includes a chemical mechanical polishing (CMP) process to increase a process margin.
A conventional method for forming a self-aligned contact pad includes depositing a polysilicon layer, etching back the polysilicon layer, and performing a CMP process using a CMP slurry for an oxide layer to form a DC pad and a BC pad.
FIGS. 1A
to
1
E illustrate cross-sectional views of a conventional process of forming a self-aligned contact pad for use in a semiconductor device.
First, as shown in
FIG. 1A
, a semiconductor substrate
10
includes an active region
11
and a non-active region having a device isolation layer
12
. A plurality of gates
20
are formed on corresponding gate oxide layers
21
, respectively. Each of the plurality of gates
20
includes a polysilicon layer
22
and a tungsten silicide layer
23
sequentially stacked on the gate oxide layer
21
. A nitride layer is formed on a corresponding tungsten silicide layer
23
as a gate mask
30
. Thereafter, a nitride spacer
40
is formed on both sidewalls of the gate
20
and the gate mask
30
.
As shown in
FIG. 1B
, an interlayer insulating layer
50
is deposited over the entire surface of the semiconductor substrate
10
and then etched to form an opening
51
. In a subsequent process, DC pads and BC pads will be formed on portions of the active region exposed by the opening
51
. The interlayer insulating layer
50
is made of a high-density plasma (HDP) oxide layer.
Subsequently, as shown in
FIG. 1C
, a polysilicon layer
60
is deposited over the entire surface of the semiconductor substrate
10
.
Then, as shown in
FIG. 1D
, the polysilicon layer
60
is etched-back to electrically insulate the contact pads until the HDP oxide interlayer insulating layer
50
is exposed, so that the polysilicon layer
60
remains in the opening
51
. Thereafter, the HDP oxide interlayer insulating layer
50
is over-etched by, for example, 500 Å.
As shown in
FIG. 1E
, the HDP oxide interlayer insulating layer
50
and the polysilicon layer (
60
of
FIG. 1D
) are planarized by a CMP process to electrically insulate the contact pads, thereby forming the contact pads, i.e., DC pads
61
that are bit line self-aligned contact pads and BC pads
62
that are storage node self-aligned contact pads.
However, the conventional method of forming the self-aligned contact pads has the following disadvantages. When the HDP oxide interlayer insulating layer
50
is over-etched, flat zones of a wafer are etched more than other areas due to a uniformity property of dry etching equipment. This excessive over-etching of flat zones of a wafer causes the gate mask
30
of chips on the flat zone of the wafer to be exposed. Since the CMP process is performed in this state, more of the nitride layer
30
(i.e., gate mask) is consumed, and the nitride layer
30
becomes relatively thin. For example, the nitride layer
30
has an average thickness of about 500 Å, but the nitride layer
30
of the chips on the flat zone of the wafer, e.g., a portion of the nitride layer
30
, indicated by reference numeral
70
in
FIG. 1E
, may be over-etched by 250 Å or more. This over-etching may result in a portion of the gate
30
being exposed, thereby causing a defect such as a short circuit between the gate
20
and the contact pads
61
and
62
.
SUMMARY OF THE INVENTION
To overcome the problems described above, a preferred embodiment of the present invention provides a method of forming a self-aligned contact pad, which may prevent defects such as a short circuit between a gate and a contact pad.
In order to provide the above-mentioned feature, a preferred embodiment of the present invention provides a method of forming a self-aligned contact pad for use in a semiconductor device. The method includes: forming a gate having a gate mask formed thereon on a semiconductor substrate, the semiconductor substrate including an active region and a non-active region, forming a spacer on both sidewalls of the gate and the gate mask, forming an interlayer insulating layer over the entire surface of the semiconductor substrate, the interlayer insulating layer including an opening formed on the active region of the semiconductor substrate, forming a conductive material layer over the entire surface of the semiconductor substrate to cover the interlayer insulating layer, etching-back the conductive material layer until the interlayer insulating layer is exposed, and performing a multi-step CMP process to form contact pads in the opening of the interlayer insulating layer, such that the contact pads are electrically insulated from each other.
Preferably, the multi-step CMP process includes a first CMP process for etching the conductive material layer and the interlayer insulating layer using a first slurry; and a second CMP process for etching the conductive material layer using a second slurry, wherein the second slurry has a higher selectivity in the conductive material layer than in the gate mask to form the contact pads.
The first CMP process is preferably performed using the first slurry until the gate mask is exposed. The first slurry is preferably an oxide slurry such that an etching selectivity ratio of the gate mask, the conductive material layer and the interlayer insulating layer is 1:2:2. The gate mask is preferably a nitride layer, the conductive material layer is preferably a polysilicon layer, and the interlayer insulating layer is preferably a high density plasma (HDP) oxide layer.
In the second CMP process, a width of the gate mask exposed between the contact pads is preferably at least 30 nm, and a thickness of the gate mask is preferably at least 300 Å. The second slurry is preferably a poly slurry such that an etching selectivity ratio of the gate mask and the polysilicon layer is 1:50. The gate mask is preferably a nitride layer, the conductive material layer is preferably a polysilicon layer, and the interlayer insulating layer is preferably a HDP oxide layer. After etching-back the conductive material layer until the interlayer insulating layer is exposed, the method may further include over-etching the interlayer insulating layer. The gate may include a gate oxide layer, a polysilicon layer and a tungsten silicide layer sequentially stacked on the semiconductor substrate.
In a method of the present invention, the self-aligned contact pads are formed using a multi-step CMP process, i.e., a two-step CMP process, and therefore excessive consumption of the nitride layer may be prevented, thereby preventing a defect such as a short circuit between the gate and the contact pads.


REFERENCES:
patent: 5707883 (1998-01-01), Tabara
patent: 6337275 (2002-01-01), Cho et al.
patent: 6455381 (2002-09-01), Shimizu et al.

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