Method of forming a self-aligned contact of a DRAM cell

Details Method of forming a self-aligned contact of a DRAM cell Method of forming a self-aligned contact of a DRAM cell

1997-03-27

1999-03-23

Brown, Peter Toby

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438639, 438396, 438586, H01L 218242

Patent

active

058858954

ABSTRACT:
A method of forming a self-aligned contact of a DRAM cell includes providing a substrate having a MOS transistor. The MOS transistor includes a gate and a source/drain region. A first insulating layer, a second insulating layer and a third insulating layer are formed over the surface of the substrate in succession. The third insulating layer is planarized. A contact window mask is formed above the third insulating layer. Using the contact window mask as a cover, the third insulating layer is removed using anisotropic dry etching and isotropic wet etching. Then, a portion of the second insulating layer and a portion of the first insulating layer are removed sequentially to expose the source/drain region so that a self-aligned contact is formed.

REFERENCES:
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5356834 (1994-10-01), Sugimoto et al.
patent: 5413961 (1995-05-01), Kim
patent: 5668052 (1997-09-01), Matsumoto et al.

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